X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fintel%2Fi3100%2Framinit.c;h=926d5b3afbe3207089dcab1bdeadd9825931af24;hb=c5fc7db3559e080858461b724251f87be6faa2cd;hp=6778491b8ef1f41e37bce805bf0e6042b81a3bcf;hpb=a9faea8977cae2c1c55b83b214aee6845de1c885;p=coreboot.git diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 6778491b8..926d5b3af 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman * Copyright (C) 2008 Arastra, Inc. * * This program is free software; you can redistribute it and/or modify @@ -18,11 +19,9 @@ * */ -/* This code is based on src/northbridge/intel/e7520/raminit.c */ - -#include #include #include +#include #include "raminit.h" #include "i3100.h" @@ -65,7 +64,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; u32 where; @@ -77,7 +76,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } struct dimm_size { @@ -89,7 +88,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, ddr2; + int value, low; sz.side1 = 0; sz.side2 = 0; @@ -150,12 +149,12 @@ static struct dimm_size spd_get_dimm_size(u16 device) goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; sz.side2 = 0; - out: +out: return sz; } @@ -278,11 +277,11 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; - out: +out: return dra; } @@ -529,7 +528,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -557,7 +556,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, continue; } value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */ - if (value != 2) die("ERROR - Non ECC memory dimm\r\n"); + if (value != 2) die("ERROR - Non ECC memory dimm\n"); value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ value &= 0x0f; /* clip self refresh bit */ @@ -595,12 +594,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, goto out; - val_err: - die("Bad SPD value\r\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; - out: +out: return drc; } @@ -611,7 +608,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -684,12 +681,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DDR2ODTC, data32); @@ -716,7 +713,6 @@ static void set_receive_enable(const struct mem_controller *ctrl) u32 dimm; u32 edge; int32_t data32; - u32 data32_dram; u32 dcal_data32_0; u32 dcal_data32_1; u32 dcal_data32_2; @@ -922,7 +918,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(MCBAR+DCALDATA+(16*4), 0x00000000); @@ -948,11 +944,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) u32 drc; u32 data32; u32 mode_reg; - u32 *iptr; - volatile u32 *iptrv; - msr_t msr; - u32 scratch; - u8 byte; + const u32 *iptr; u16 data16; static const struct { u32 clkgr[4]; @@ -963,8 +955,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}}, /* FSB 167 */ {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}}, - /* N/A */ - {{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}}, + /* FSB 200 DIMM 400 */ + {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; static const u32 dqs_data[] = { @@ -978,19 +970,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ -#ifdef DIMM_MAP_LOGICAL pci_write_config32(ctrl->f0, DRM, - 0x00410000 | DIMM_MAP_LOGICAL); -#else - pci_write_config32(ctrl->f0, DRM, 0x00411248); -#endif + 0x00410000 | CONFIG_DIMM_MAP_LOGICAL); /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 & ~(7 << 8); /* clear refresh rates */ @@ -1025,16 +1013,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<8;i+=2) { /* loop through each dimm to test */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Apply NOP */ @@ -1042,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1052,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1063,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* fixme hard code AL additive latency */ write32(MCBAR+DCALADDR, 0x0b940001); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1076,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, mode_reg); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1088,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1139,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1149,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (0x0b940001)); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); @@ -1178,16 +1156,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(MCBAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(MCBAR+DCALDATA+i, 0x00000000); } for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ @@ -1195,13 +1172,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 |= (1 << 31); pci_write_config32(ctrl->f0, 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(ctrl->f0, 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ @@ -1220,5 +1197,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ +#if CONFIG_CACHE_AS_RAM == 0 cache_lbmem(MTRR_TYPE_WRBACK); +#endif }