X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fintel%2Fi3100%2Framinit.c;h=926d5b3afbe3207089dcab1bdeadd9825931af24;hb=c5fc7db3559e080858461b724251f87be6faa2cd;hp=242dcf9105ac89fb93c88912f9e5ad970dbab3c3;hpb=5d3dee8334c2303434d7b00bec3aad4911120ac1;p=coreboot.git diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 242dcf910..926d5b3af 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -154,7 +154,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) hw_err: sz.side1 = 0; sz.side2 = 0; - out: +out: return sz; } @@ -281,7 +281,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; - out: +out: return dra; } @@ -597,7 +597,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; - out: +out: return drc; } @@ -944,7 +944,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) u32 drc; u32 data32; u32 mode_reg; - u32 *iptr; + const u32 *iptr; u16 data16; static const struct { u32 clkgr[4]; @@ -973,12 +973,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("Starting SDRAM Enable\n"); /* 0x80 */ -#ifdef DIMM_MAP_LOGICAL pci_write_config32(ctrl->f0, DRM, - 0x00410000 | DIMM_MAP_LOGICAL); -#else - pci_write_config32(ctrl->f0, DRM, 0x00411248); -#endif + 0x00410000 | CONFIG_DIMM_MAP_LOGICAL); /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { @@ -1024,9 +1020,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Apply NOP */ @@ -1034,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1044,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1055,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* fixme hard code AL additive latency */ write32(MCBAR+DCALADDR, 0x0b940001); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1068,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, mode_reg); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1080,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1131,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1141,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (0x0b940001)); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); @@ -1177,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ @@ -1212,7 +1197,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ -#if CONFIG_USE_DCACHE_RAM == 0 +#if CONFIG_CACHE_AS_RAM == 0 cache_lbmem(MTRR_TYPE_WRBACK); #endif }