X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fintel%2Fe7520%2Framinit.c;h=d226085d0d834cb86ad47c571f323b3ee95f169b;hb=c5fc7db3559e080858461b724251f87be6faa2cd;hp=e9827c43b99446a004855e002a4c0acddde85139;hpb=7fd931b11d6727f489f8ed76530b43a382ed3c60;p=coreboot.git diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index e9827c43b..d226085d0 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -15,7 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include @@ -81,8 +80,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) print_spew("done.\n"); } - - struct dimm_size { unsigned long side1; unsigned long side2; @@ -164,7 +161,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) hw_err: sz.side1 = 0; sz.side2 = 0; - out: +out: return sz; } @@ -209,7 +206,6 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) return 0; } - static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) { unsigned dimm_mask; @@ -236,7 +232,6 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) return dimm_mask; } - static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -291,12 +286,11 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; - out: +out: return dra; } - static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { @@ -624,7 +618,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, } ecc = 2; #if CONFIG_HAVE_OPTION_TABLE - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (read_option(ECC_memory, 1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); } else @@ -664,7 +658,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; - out: +out: return drc; } @@ -798,6 +792,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } } } + static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -1030,7 +1025,6 @@ static void set_receive_enable(const struct mem_controller *ctrl) write32(BAR+0x154, recenb); } - static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; @@ -1084,12 +1078,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("Starting SDRAM Enable\n"); /* 0x80 */ -#ifdef DIMM_MAP_LOGICAL pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, - 0x00210000 | DIMM_MAP_LOGICAL); -#else - pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248); -#endif + 0x00210000 | CONFIG_DIMM_MAP_LOGICAL); /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { @@ -1138,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+0x100, (0x83000000 | (i<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } @@ -1149,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1162,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1176,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1197,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1212,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1263,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1274,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (0x0b940001)); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } } @@ -1320,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */