X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fintel%2Fe7520%2Framinit.c;h=d226085d0d834cb86ad47c571f323b3ee95f169b;hb=c5fc7db3559e080858461b724251f87be6faa2cd;hp=bb4ebbdfe37d1fa81a0ae55793598f5fdb91ec15;hpb=ed15220b87d298088a074747b24e212c23333e33;p=coreboot.git

diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index bb4ebbdfe..d226085d0 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -15,7 +15,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
  */
 
 #include <cpu/x86/mtrr.h>
@@ -23,6 +22,10 @@
 #include <stdlib.h>
 #include "raminit.h"
 #include "e7520.h"
+#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
 
 #define BAR 0x40000000
 
@@ -33,13 +36,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		/* CKDIS 0x8c disable clocks */
 	PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
 
-		/* 0x9c Device present and extended RAM control 
+		/* 0x9c Device present and extended RAM control
 		 * DEVPRES is very touchy, hard code the initialization
 		 * of PCI-E ports here.
 		 */
 	PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
 
-		/* 0xc8 Remap RAM base and limit off */	
+		/* 0xc8 Remap RAM base and limit off */
 	PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
 
 		/* ??? */
@@ -57,7 +60,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
 
 		/* 0x14 */
-	PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,  
+	PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
 	};
 	int i;
 	int max;
@@ -67,18 +70,16 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		device_t dev;
 		unsigned where;
 		unsigned long reg;
-		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
+		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + PCI_DEV(0, 0x00, 0);
 		where = register_values[i] & 0xff;
 		reg = pci_read_config32(dev, where);
 		reg &= register_values[i+1];
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 }
 
-
-
 struct dimm_size {
 	unsigned long side1;
 	unsigned long side2;
@@ -122,7 +123,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
 	if (value < 0) goto hw_err;
 	value &= 0xff;
 	value <<= 8;
-	
+
 	low = spd_read_byte(device, 6);	/* (low byte) */
 	if (low < 0) goto hw_err;
 	value = value | (low & 0xff);
@@ -155,12 +156,12 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	sz.side1 = 0;
 	sz.side2 = 0;
- out:
+out:
 	return sz;
 
 }
@@ -169,7 +170,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 {
 	int i;
 	int cum;
-	
+
 	for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 		struct dimm_size sz;
 		if (dimm_mask & (1 << i)) {
@@ -181,31 +182,30 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 			sz.side1 -= 29;
 			cum += (1 << sz.side1);
 			/* DRB = 0x60 */
-			pci_write_config8(ctrl->f0, DRB + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
 			if( sz.side2 > 28) {
 				sz.side2 -= 29;
 				cum += (1 << sz.side2);
 			}
-			pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
 		}
 		else {
-			pci_write_config8(ctrl->f0, DRB + (i*2), cum);
-			pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
 		}
 	}
 	/* set TOM top of memory 0xcc */
-	pci_write_config16(ctrl->f0, TOM, cum);
+	pci_write_config16(PCI_DEV(0, 0x00, 0), TOM, cum);
 	/* set TOLM top of low memory */
 	if(cum > 0x18) {
 		cum = 0x18;
 	}
 	cum <<= 11;
 	/* 0xc4 TOLM */
-	pci_write_config16(ctrl->f0, TOLM, cum);
+	pci_write_config16(PCI_DEV(0, 0x00, 0), TOLM, cum);
 	return 0;
 }
 
-
 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 {
 	unsigned dimm_mask;
@@ -232,8 +232,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 	return dimm_mask;
 }
 
-
-static int spd_set_row_attributes(const struct mem_controller *ctrl, 
+static int spd_set_row_attributes(const struct mem_controller *ctrl,
 		long dimm_mask)
 {
 
@@ -264,36 +263,35 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 		reg += log2(value & 0xff);
 
 		/* Get the device width and convert it to a power of two */
-		value = spd_read_byte(ctrl->channel0[cnt], 13);	
+		value = spd_read_byte(ctrl->channel0[cnt], 13);
 		if (value < 0) goto hw_err;
 		value = log2(value & 0xff);
 		reg += value;
 		if(reg < 27) goto hw_err;
 		reg -= 27;
 		reg += (value << 2);
-	
+
 		dra += reg << (cnt*8);
 		value = spd_read_byte(ctrl->channel0[cnt], 5);
 		if (value & 2)
-			dra += reg << ((cnt*8)+4);	
+			dra += reg << ((cnt*8)+4);
 	}
 
 	/* 0x70 DRA */
-	pci_write_config32(ctrl->f0, DRA, dra);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra);
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	dra = 0;
- out:
+out:
 	return dra;
 
 }
 
-
-static int spd_set_drt_attributes(const struct mem_controller *ctrl, 
+static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		long dimm_mask, uint32_t drc)
 {
 	int value;
@@ -305,23 +303,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 	int latency;
 	uint32_t index = 0;
 	uint32_t index2 = 0;
-	static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; 
+	static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
 	static const int latency_indicies[] = { 26, 23, 9 };
 
 	/* 0x78 DRT */
-	drt = pci_read_config32(ctrl->f0, DRT);
+	drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT);
 	drt &= 3;  /* save bits 1:0 */
-	
+
 	for(first_dimm = 0; first_dimm < 4; first_dimm++) {
-		if (dimm_mask & (1 << first_dimm)) 
+		if (dimm_mask & (1 << first_dimm))
 			break;
 	}
-	
+
 	/* get dimm type */
 	value = spd_read_byte(ctrl->channel0[first_dimm], 2);
 	if(value == 8) {
 		drt |= (3<<5); /* back to bark write turn around & cycle add */
-	}	
+	}
 
 	drt |= (3<<18);  /* Trasmax */
 
@@ -332,22 +330,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 		/* Compute the lowest cas latency supported */
 		latency = log2(reg) -2;
-	
+
 		/* Loop through and find a fast clock with a low latency */
 		for(index = 0; index < 3; index++, latency++) {
 			if ((latency < 2) || (latency > 4) ||
 				(!(reg & (1 << latency)))) {
 				continue;
 			}
-			value = spd_read_byte(ctrl->channel0[cnt], 
+			value = spd_read_byte(ctrl->channel0[cnt],
 				        latency_indicies[index]);
-	  
+
 			if(value <= cycle_time[drc&3]) {
 				if( latency > cas_latency) {
 					cas_latency = latency;
 				}
 				break;
-			}	
+			}
 		}
 	}
 	index = (cas_latency-2);
@@ -401,7 +399,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<8);  /* Trp RAS Precharg */
 		}
-		
+
 		/* Trcd RAS to CAS delay */
 		if((index2&0x0ff)<=0x03c) {
 			drt |= (0<<10);
@@ -411,7 +409,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 
 		/* Tdal Write auto precharge recovery delay */
 		drt |= (1<<12);
-	
+
 		/* Trc TRS min */
 		if((index2&0x0ff00)<=0x03700)
 			drt |= (0<<14);
@@ -419,9 +417,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 			drt |= (1<<14);
 		else
 			drt |= (2<<14); /* spd 41 */
-		
+
 		drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
-		
+
 		/* Trrd Row Delay */
 		if((index&0x0ff0000)<=0x0140000) {
 			drt |= (0<<20);
@@ -432,7 +430,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (3<<20);
 		}
-		
+
 		/* Trfc Auto refresh cycle time */
 		if((index2&0x0ff0000)<=0x04b0000) {
 			drt |= (0<<22);
@@ -446,14 +444,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 	}
 	else if(value <= 0x60) { /* 167 Mhz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz 
+		 * for bits 3:2 for all 167 Mhz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
 		} else {
 			drt |= (2<<8);  /* Trp RAS Precharg */
 		}
-		
+
 		/* Trcd RAS to CAS delay */
 		if((index2&0x0ff)<=0x030) {
 			drt |= (0<<10);
@@ -462,13 +460,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		}
 
 		/* Tdal Write auto precharge recovery delay */
-		drt |= (2<<12); 
-		
+		drt |= (2<<12);
+
 		/* Trc TRS min */
 		drt |= (2<<14); /* spd 41, but only one choice */
-		
+
 		drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
-		
+
 		/* Trrd Row Delay */
 		if((index&0x0ff0000)<=0x0180000) {
 			drt |= (0<<20);
@@ -477,7 +475,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<20);
 		}
-		
+
 		/* Trfc Auto refresh cycle time */
 		if((index2&0x0ff0000)<=0x0480000) {
 			drt |= (0<<22);
@@ -505,13 +503,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		}
 
 		/* Tdal Write auto precharge recovery delay */
-		drt |= (1<<12); 
-		
+		drt |= (1<<12);
+
 		/* Trc TRS min */
 		drt |= (2<<14); /* spd 41, but only one choice */
-		
+
 		drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
-		
+
 		/* Trrd Row Delay */
 		if((index&0x0ff0000)<=0x01e0000) {
 			drt |= (0<<20);
@@ -520,7 +518,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<20);
 		}
-		
+
 		/* Trfc Auto refresh cycle time */
 		if((index2&0x0ff0000)<=0x04b0000) {
 			drt |= (0<<22);
@@ -529,25 +527,25 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		
+
 		/* Based on CAS latency */
 		if(index&7)
 			drt |= (0x099<<24);
 		else
 			drt |= (0x055<<24);
-		
+
 	}
 	else {
-		die("Invalid SPD 9 bus speed.\r\n");
+		die("Invalid SPD 9 bus speed.\n");
 	}
 
 	/* 0x78 DRT */
-	pci_write_config32(ctrl->f0, DRT, drt);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRT, drt);
 
 	return(cas_latency);
 }
 
-static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, 
+static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 		long dimm_mask)
 {
 	int value;
@@ -558,12 +556,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	unsigned char dram_type = 0xff;
 	unsigned char ecc = 0xff;
 	unsigned char rate = 62;
-	static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; 
+	static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
 	static const unsigned char drc_rates[5] = {0,15,7,62,3};
 	static const unsigned char fsb_conversion[4] = {3,1,3,2};
 
 	/* 0x7c DRC */
-	drc = pci_read_config32(ctrl->f0, DRC);	
+	drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC);
 	for(cnt=0; cnt < 4; cnt++) {
 		if (!(dimm_mask & (1 << cnt))) {
 			continue;
@@ -576,23 +574,23 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 					ecc = 2;
 				}
 				else if (ecc == 1) {
-					die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+					die("ERROR - Mixed DDR & DDR2 RAM\n");
 				}
-			} 
+			}
 			else if ( reg == 7 ) {
 				if ( ecc == 0xff) {
 					ecc = 1;
 				}
 				else if ( ecc > 1 ) {
-					die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+					die("ERROR - Mixed DDR & DDR2 RAM\n");
 				}
-			}	
+			}
 			else {
-				die("ERROR - RAM not DDR\r\n");
+				die("ERROR - RAM not DDR\n");
 			}
 		}
 		else {
-			die("ERROR - Non ECC memory dimm\r\n");
+			die("ERROR - Non ECC memory dimm\n");
 		}
 
 		value = spd_read_byte(ctrl->channel0[cnt], 12);	/*refresh rate*/
@@ -619,12 +617,14 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 
 	}
 	ecc = 2;
-	if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
+#if CONFIG_HAVE_OPTION_TABLE
+	if (read_option(ECC_memory, 1) == 0) {
 		ecc = 0;  /* ECC off in CMOS so disable it */
-		print_debug("ECC off\r\n");
-	}
-	else {
-		print_debug("ECC on\r\n");
+		print_debug("ECC off\n");
+	} else
+#endif
+	{
+		print_debug("ECC on\n");
 	}
 	drc &= ~(3 << 20); /* clear the ecc bits */
 	drc |= (ecc << 20);  /* or in the calculated ecc bits */
@@ -650,26 +650,26 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	drc |= (fsb_conversion[value] << 2);
 	drc &= ~(3 << 0); /* set the dram type */
 	drc |= (dram_type << 0);
-		
+
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	drc = 0;
- out:
+out:
 	return drc;
 }
 
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	long dimm_mask;
 
 	/* Test if we can read the spd and if ram is ddr or ddr2 */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -681,7 +681,7 @@ static void do_delay(void)
 	unsigned char b;
 	for(i=0;i<16;i++)
 		b=inb(0x80);
-}	
+}
 
 static void pll_setup(uint32_t drc)
 {
@@ -710,7 +710,7 @@ static void pll_setup(uint32_t drc)
 	}
 	mainboard_set_e7520_pll(pins);
 	return;
-}	
+}
 
 #define TIMEOUT_LOOPS 300000
 
@@ -724,15 +724,15 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
         unsigned int dimm,i;
         unsigned int data32;
 	unsigned int t4;
- 
+
 	/* Set up northbridge values */
 	/* ODT enable */
-  	pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
+  	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180);
 	/* Figure out which slots are Empty, Single, or Double sided */
 	for(i=0,t4=0,c2=0;i<8;i+=2) {
-		c1 = pci_read_config8(ctrl->f0, DRB+i);
+		c1 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+i);
 		if(c1 == c2) continue;
-		c2 = pci_read_config8(ctrl->f0, DRB+1+i);
+		c2 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+1+i);
 		if(c1 == c2)
 			t4 |= (1 << (i*4));
 		else
@@ -741,10 +741,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 	for(i=0;i<1;i++) {
 	    if((t4&0x0f) == 1) {
 		if( ((t4>>8)&0x0f) == 0 ) {
-			data32 = 0x00000010; /* EEES */ 
+			data32 = 0x00000010; /* EEES */
 			break;
 		}
-		if ( ((t4>>16)&0x0f) == 0 ) { 
+		if ( ((t4>>16)&0x0f) == 0 ) {
 			data32 = 0x00003132; /* EESS */
 			break;
 		}
@@ -757,7 +757,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 	    }
 	    if((t4&0x0f) == 2) {
 		if( ((t4>>8)&0x0f) == 0 ) {
-			data32 = 0x00003132; /* EEED */ 
+			data32 = 0x00003132; /* EEED */
 			break;
 		}
 		if ( ((t4>>8)&0x0f) == 2 ) {
@@ -771,27 +771,28 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 		data32 = 0x777becdc; /* ESSD */
 		break;
 	    }
-	    die("Error - First dimm slot empty\r\n");
+	    die("Error - First dimm slot empty\n");
 	}
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
-  	pci_write_config32(ctrl->f0, 0xb0, data32);
+  	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
 
 	for(dimm=0;dimm<8;dimm+=1) {
 
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
-		
+
 		for(i=0;i<1001;i++) {
 			data32 = read32(BAR+DCALCSR);
 			if(!(data32 & (1<<31)))
 				break;
 		}
 	}
-}	
+}
+
 static void set_receive_enable(const struct mem_controller *ctrl)
 {
 	unsigned int i;
@@ -799,7 +800,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 	uint32_t recena=0;
 	uint32_t recenb=0;
 
-	{	
+	{
 	unsigned int dimm;
 	unsigned int edge;
 	int32_t data32;
@@ -817,7 +818,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 		if(!(dimm&1)) {
 			write32(BAR+DCALDATA+(17*4), 0x04020000);
 			write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
-		
+
 			for(i=0;i<1001;i++) {
 				data32 = read32(BAR+DCALCSR);
 				if(!(data32 & (1<<31)))
@@ -825,7 +826,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 			}
 			if(i>=1000)
 				continue;
-		
+
 			dcal_data32_0 = read32(BAR+DCALDATA + 0);
 			dcal_data32_1 = read32(BAR+DCALDATA + 4);
 			dcal_data32_2 = read32(BAR+DCALDATA + 8);
@@ -914,7 +915,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 				data32++;
 			}
 			/* test for frame edge cross overs */
-			if((edge == 1) && (data32 > 12) && 
+			if((edge == 1) && (data32 > 12) &&
 			    (((recen+16)-data32) < 3)) {
 				data32 = 0;
 				cnt += 2;
@@ -1009,7 +1010,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 	print_debug_hex32(recena);
 	print_debug(",  Receive enable B = ");
 	print_debug_hex32(recenb);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* clear out the calibration area */
 	write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1024,7 +1025,6 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 	write32(BAR+0x154, recenb);
 }
 
-
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
 	int i;
@@ -1063,31 +1063,27 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		/* FSB 200 DIMM 400 */
 	{{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
 	};
-	
+
 	static const uint32_t dqs_data[] = {
-		0xffffffff, 0xffffffff, 0x000000ff, 
-		0xffffffff, 0xffffffff, 0x000000ff, 
+		0xffffffff, 0xffffffff, 0x000000ff,
+		0xffffffff, 0xffffffff, 0x000000ff,
 		0xffffffff, 0xffffffff,	0x000000ff,
 		0xffffffff, 0xffffffff, 0x000000ff,
-		0xffffffff, 0xffffffff, 0x000000ff, 
-		0xffffffff, 0xffffffff, 0x000000ff, 
-		0xffffffff, 0xffffffff, 0x000000ff, 
+		0xffffffff, 0xffffffff, 0x000000ff,
+		0xffffffff, 0xffffffff, 0x000000ff,
+		0xffffffff, 0xffffffff, 0x000000ff,
 		0xffffffff, 0xffffffff, 0x000000ff};
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
-	pci_write_config32(ctrl->f0, DRM,
-		0x00210000 | DIMM_MAP_LOGICAL);
-#else
-	pci_write_config32(ctrl->f0, DRM, 0x00211248);
-#endif
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
+		0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if( drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	pll_setup(drc);
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
@@ -1097,82 +1093,78 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
   	/* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
   	for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
 			cnt<4;cnt++) {
-  		pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
+  		pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]);
 	}
 	/* 0x7c DRC */
-  	pci_write_config32(ctrl->f0, DRC, data32);
-	
+  	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
+
 		/* turn the clocks on */
 	/* 0x8c CKDIS */
-  	pci_write_config16(ctrl->f0, CKDIS, 0x0000);
-	
+  	pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000);
+
 		/* 0x9a DDRCSR Take subsystem out of idle */
-  	data16 = pci_read_config16(ctrl->f0, DDRCSR);
+  	data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR);
 	data16 &= ~(7 << 12);
 	data16 |= (3 << 12);   /* use dual channel lock step */
-  	pci_write_config16(ctrl->f0, DDRCSR, data16);
-	
+  	pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16);
+
 		/* program row size DRB */
 	spd_set_ram_size(ctrl, mask);
 
 		/* program page size DRA */
 	spd_set_row_attributes(ctrl, mask);
 
-		/* program DRT timing values */	
+		/* program DRT timing values */
 	cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
 
 	for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
 		print_debug("DIMM ");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		/* Apply NOP */
 		do_delay();
-		
+
 		write32(BAR + 0x100, (0x03000000 | (i<<20)));
 
 		write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 
 	}
-	
+
 	/* Apply NOP */
 	do_delay();
 
-	for(cs=0;cs<8;cs++) {	
-		write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); 
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+	for(cs=0;cs<8;cs++) {
+		write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		if ((drc & 3) == 2) /* DDR2  */
                         write32(BAR+DCALADDR, 0x04000000);
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
-		
+
 	/* EMRS dll's enabled */
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		if ((drc & 3) == 2) /* DDR2  */
 			/* fixme hard code AL additive latency */
                         write32(BAR+DCALADDR, 0x0b940001);
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
@@ -1188,78 +1180,73 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else  /*  CAS Latency 2.5 */
                         mode_reg = 0x016a0000;
         }
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
 	do_delay();
 	do_delay();
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		if ((drc & 3) == 2) /* DDR2  */
                         write32(BAR+DCALADDR, 0x04000000);
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
 		write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
-	
+
 	/* Do 2 refreshes */
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
 	}
 	do_delay();
 	/* MRS reset dll's normal */
 	do_delay();
-	for(cs=0;cs<8;cs++) {	
+	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
@@ -1268,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-			data32 = read32(BAR+DCALCSR);
-			while(data32 & 0x80000000)
-				data32 = read32(BAR+DCALCSR);
+			do data32 = read32(BAR+DCALCSR);
+			while(data32 & 0x80000000);
                 }
         }
 
@@ -1279,7 +1265,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	write32(BAR+DCALCSR, 0x0000000f);
 
 	/* DDR1 This is test code to copy some codes in the factory setup */
-	
+
 	write32(BAR, 0x00100000);
 
         if ((drc & 3) == 2) { /* DDR2  */
@@ -1287,66 +1273,65 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		set_on_dimm_termination_enable(ctrl);
 	}
 	else { /* ddr */
-                pci_write_config32(ctrl->f0, 0x88, 0xa0000000 );
+                pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 );
         }
 
 	/* receive enable calibration */
 	set_receive_enable(ctrl);
-	
+
 	/* DQS */
-	pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); 
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
 	for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
 		write32(cnt, dqs_data[i]);
 	}
-	pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
 
 	/* Enable refresh */
 	/* 0x7c DRC */
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
-	pci_write_config32(ctrl->f0, DRC, data32);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
 	write32(BAR+DCALCSR, 0x0008000f);
 
 	/* clear memory and init ECC */
-	print_debug("Clearing memory\r\n");
+	print_debug("Clearing memory\n");
 	for(i=0;i<64;i+=4) {
 		write32(BAR+DCALDATA+i, 0x00000000);
 	}
-	
+
 	for(cs=0;cs<8;cs++) {
 		write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-		data32 = read32(BAR+DCALCSR);
-		while(data32 & 0x80000000)
-			data32 = read32(BAR+DCALCSR);
+		do data32 = read32(BAR+DCALCSR);
+		while(data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
-	data32 = pci_read_config32(ctrl->f0, 0x98);
+	data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
 	data32 |= (1 << 31);
-	pci_write_config32(ctrl->f0, 0x98, data32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
 	/* wait for completion */
-	print_debug("Waiting for mem complete\r\n");
+	print_debug("Waiting for mem complete\n");
 	while(1) {
-		data32 = pci_read_config32(ctrl->f0, 0x98);
+		data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
 		if( (data32 & (1<<31)) == 0)
 			break;
 	}
-	print_debug("Done\r\n");
-	
+	print_debug("Done\n");
+
 	/* Set initialization complete */
 	/* 0x7c DRC */
 	drc |= (1 << 29);
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
-	pci_write_config32(ctrl->f0, DRC, data32);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
 
 	/* Set the ecc mode */
-	pci_write_config32(ctrl->f0, DRC, drc);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc);
 
 	/* Enable memory scrubbing */
-	/* 0x52 MCHSCRB */	
-	data16 = pci_read_config16(ctrl->f0, MCHSCRB);
+	/* 0x52 MCHSCRB */
+	data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB);
 	data16 &= ~0x0f;
 	data16 |= ((2 << 2) | (2 << 0));
-	pci_write_config16(ctrl->f0, MCHSCRB, data16);	
+	pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16);
 
 	/* The memory is now setup, use it */
 	cache_lbmem(MTRR_TYPE_WRBACK);