X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Flx%2Fpll_reset.c;h=3077b61c9caa5bccbf19816a8b3648a54da983c9;hb=8cf54c9f236afef6b74b6510983bd25e8536055a;hp=1f8e499825607b06d7a31969110a5ba7c72dba92;hpb=f1939bb29b15cb68e90c68ceda86d8d9ad20e746;p=coreboot.git

diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 1f8e49982..3077b61c9 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -59,9 +59,8 @@ static void pll_reset(char manualconf)
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
 		/* You should never get here..... The chip has reset. */
-		printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
 		post_code(POST_PLL_RESET_FAIL);
-		__asm__ __volatile__("hlt\n");
+		die("CONFIGURING PLL FAILURE\n");
 
 	}
 	printk(BIOS_DEBUG, "PLL configured.\n");