X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Fgx1%2Fnorthbridge.c;h=9fa5e33cff38438785a18730e49c18b8901fad0e;hb=4b42a62966527f18f3894af953b0757080424b00;hp=4eb02c7dedfa50fbd3d212513f286234c464adcf;hpb=9fe4d797a37671a65053add3f7cca27397db0b9b;p=coreboot.git

diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 4eb02c7de..9fa5e33cf 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -40,13 +40,13 @@ static void enable_shadow(device_t dev)
        write32(GX_BASE+BC_XMAP_3, 0x77777777);
 }
 
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
-	printk_debug("northbridge: %s()\n", __func__);
-	
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
+
 	optimize_xbus(dev);
 	enable_shadow(dev);
-	printk_spew("Calling enable_cache()\n");
+	printk(BIOS_SPEW, "Calling enable_cache()\n");
 	enable_cache();
 }
 
@@ -63,48 +63,9 @@ static struct device_operations northbridge_operations = {
 static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops = &northbridge_operations,
 	.vendor = PCI_VENDOR_ID_CYRIX,
-	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
+	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
 };
 
-static void ram_resource(device_t dev, unsigned long index,
-        unsigned long basek, unsigned long sizek)
-{
-        struct resource *resource;
-
-        if (!sizek) {
-                return;
-        }
-        resource = new_resource(dev, index);
-        resource->base  = ((resource_t)basek) << 10;
-        resource->size  = ((resource_t)sizek) << 10;
-        resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
-                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
-	struct resource **best_p = gp;
-	struct resource *best;
-	best = *best_p;
-	if (!best || (best->base > new->base)) {
-		best = new;
-	}
-	*best_p = best;
-}
-
-static uint32_t find_pci_tolm(struct bus *bus)
-{
-	struct resource *min;
-	uint32_t tolm;
-	min = 0;
-	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
-	tolm = 0xffffffffUL;
-	if (min && tolm > min->base) {
-		tolm = min->base;
-	}
-	return tolm;
-}
-
 #if CONFIG_WRITE_HIGH_TABLES==1
 #define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
 extern uint64_t high_tables_base, high_tables_size;
@@ -115,8 +76,8 @@ static void pci_domain_set_resources(device_t dev)
 	device_t mc_dev;
         uint32_t pci_tolm;
 
-        pci_tolm = find_pci_tolm(&dev->link[0]);
-	mc_dev = dev->link[0].children;
+        pci_tolm = find_pci_tolm(dev->link_list);
+	mc_dev = dev->link_list->children;
 	if (mc_dev) {
 		unsigned int tomk, tolmk;
 		unsigned int ramreg = 0;
@@ -132,7 +93,7 @@ static void pci_domain_set_resources(device_t dev)
 				continue;
 			ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
 		}
-			
+
 		tomk = ramreg << 10;
 
 		/* Sort out the framebuffer size */
@@ -140,10 +101,10 @@ static void pci_domain_set_resources(device_t dev)
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -163,21 +124,21 @@ static void pci_domain_set_resources(device_t dev)
 		idx = 10;
 		ram_resource(dev, idx++, 0, tolmk);
 	}
-	assign_resources(&dev->link[0]);
+	assign_resources(dev->link_list);
 }
 
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,
-        .enable_resources = enable_childrens_resources,
-        .init             = 0,
+        .enable_resources = NULL,
+        .init             = NULL,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
-	initialize_cpus(&dev->link[0]);
+	printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+	initialize_cpus(dev->link_list);
 }
 
 static void cpu_bus_noop(device_t dev)
@@ -194,22 +155,22 @@ static struct device_operations cpu_bus_ops = {
 
 static void enable_dev(struct device *dev)
 {
-        printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+        printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
-        	printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
                 dev->ops = &pci_domain_ops;
 		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-        	printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         } else {
-        	printk_spew("device path type %d\n",dev->path.type);
+        	printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 	}
 }
 
 struct chip_operations northbridge_amd_gx1_ops = {
 	CHIP_NAME("AMD GX1 Northbridge")
-	.enable_dev = enable_dev, 
+	.enable_dev = enable_dev,
 };