X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Famdk8%2Framinit_f.c;h=c38d1595ae2f1ae483b0954ca0fd25f8569bf741;hb=c02b4fc9db3c3c1e263027382697b566127f66bb;hp=b24ef82b7f5bf5f23390bec5fb71037e1ccc553b;hpb=2f4979f347ea7014786934cccab10772f6a6402a;p=coreboot.git

diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index b24ef82b7..c38d1595a 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -20,7 +20,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/tsc.h>
@@ -28,28 +27,21 @@
 #include <stdlib.h>
 #include "raminit.h"
 #include "amdk8_f.h"
-#include "spd_ddr2.h"
+#include <spd_ddr2.h>
 
 #ifndef QRANK_DIMM_SUPPORT
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if CONFIG_USE_PRINTK_IN_CAR
-#else
-#error This file needs CONFIG_USE_PRINTK_IN_CAR
-#endif
-
-#define RAM_TIMING_DEBUG 0
-
-#if RAM_TIMING_DEBUG == 1
-#define printk_raminit printk_debug
+#if DEBUG_RAM_SETUP
+#define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define printk_raminit(fmt, arg...)
 #endif
 
 
-#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
-# error "CONFIG_LB_MEM_TOPK must be a power of 2"
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
 #include "amdk8_f_pci.c"
@@ -699,7 +691,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	}
 	sysinfo->ctrl_present[ctrl->node_id] = 1;
 
-	printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -712,11 +704,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
-
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
 	uint32_t dcl;
@@ -724,7 +714,6 @@ static int is_dual_channel(const struct mem_controller *ctrl)
 	return dcl & DCL_Width128;
 }
 
-
 static int is_opteron(const struct mem_controller *ctrl)
 {
 	/* Test to see if I am an Opteron.
@@ -738,7 +727,6 @@ static int is_opteron(const struct mem_controller *ctrl)
 	return !!(nbcap & NBCAP_128Bit);
 }
 
-
 static int is_registered(const struct mem_controller *ctrl)
 {
 	/* Test to see if we are dealing with registered SDRAM.
@@ -813,7 +801,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 	if (value <=4 ) value += 8; // add back to 1G to high
 	value += (27-5); // make 128MB to the real lines
 	if ( value != (sz->per_rank)) {
-		printk_err("Bad RANK Size --\n");
+		printk(BIOS_ERR, "Bad RANK Size --\n");
 		goto val_err;
 	}
 
@@ -834,7 +822,8 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 
 
 static void set_dimm_size(const struct mem_controller *ctrl,
-			 struct dimm_size *sz, unsigned index, struct mem_info *meminfo)
+			  struct dimm_size *sz, unsigned index,
+			  struct mem_info *meminfo)
 {
 	uint32_t base0, base1;
 
@@ -885,11 +874,11 @@ static void set_dimm_size(const struct mem_controller *ctrl,
 	if (base0) {
 		uint32_t dword;
 		uint32_t ClkDis0;
-#if CPU_SOCKET_TYPE == 0x10 /* L1 */
+#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */
 		ClkDis0 = DTL_MemClkDis0;
-#elif CPU_SOCKET_TYPE == 0x11 /* AM2 */
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */
 		ClkDis0 = DTL_MemClkDis0_AM2;
-#elif CPU_SOCKET_TYPE == 0x12	/* S1G1 */
+#elif CONFIG_CPU_SOCKET_TYPE == 0x12	/* S1G1 */
 		ClkDis0 = DTL_MemClkDis0_S1g1;
 #endif
 
@@ -1009,14 +998,13 @@ static long spd_set_ram_size(const struct mem_controller *ctrl,
 			return -1; /* Report SPD error */
 		}
 		set_dimm_size(ctrl, sz, i, meminfo);
-		set_dimm_cs_map (ctrl, sz, i, meminfo);
+		set_dimm_cs_map(ctrl, sz, i, meminfo);
 	}
 	return meminfo->dimm_mask;
 }
 
-
 static void route_dram_accesses(const struct mem_controller *ctrl,
-		                 unsigned long base_k, unsigned long limit_k)
+				unsigned long base_k, unsigned long limit_k)
 {
 	/* Route the addresses to the controller node */
 	unsigned node_id;
@@ -1045,7 +1033,6 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
 	}
 }
 
-
 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
 {
 	/* Error if I don't have memory */
@@ -1054,27 +1041,32 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM: 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
+	/* Now set top of memory */
 	msr_t msr;
 	if (tom_k > (4*1024*1024)) {
-		/* Now set top of memory */
+		printk_raminit("Handling memory mapped above 4 GB\n");
+		printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k);
 		msr.lo = (tom_k & 0x003fffff) << 10;
 		msr.hi = (tom_k & 0xffc00000) >> 22;
 		wrmsr(TOP_MEM2, msr);
+		printk_raminit("Correcting memory amount mapped below 4 GB\n");
 	}
 
 	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
 	 * so I can see my rom chip and other I/O devices.
 	 */
 	if (tom_k >= 0x003f0000) {
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 		if (hole_startk != 0) {
 			tom_k = hole_startk;
 		} else
 #endif
 		tom_k = 0x3f0000;
+		printk_raminit("Adjusting lower RAM end\n");
 	}
+	printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k);
 	msr.lo = (tom_k & 0x003fffff) << 10;
 	msr.hi = (tom_k & 0xffc00000) >> 22;
 	wrmsr(TOP_MEM, msr);
@@ -1161,7 +1153,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
 		csbase_inc <<=1;
 	}
 
-
 	/* Compute the initial values for csbase and csbask.
 	 * In csbase just set the enable bit and the base to zero.
 	 * In csmask set the mask bits for the size and page level interleave.
@@ -1184,11 +1175,12 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
 		csbase += csbase_inc;
 	}
 
-	printk_debug("Interleaved\n");
+	printk(BIOS_DEBUG, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << ((27-10) + bits);
 }
+
 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
 {
 	unsigned long tom;
@@ -1258,7 +1250,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
 	return (tom & ~0xff000000) << (27-10);
 }
 
-unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
+static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
 {
 	unsigned node_id;
 	unsigned end_k;
@@ -1278,7 +1270,6 @@ unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
 	return end_k;
 }
 
-
 static void order_dimms(const struct mem_controller *ctrl,
 			 struct mem_info *meminfo)
 {
@@ -1288,14 +1279,14 @@ static void order_dimms(const struct mem_controller *ctrl,
 	    CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
-	
+
 	if (!tom_k) {
 		tom_k = order_chip_selects(ctrl);
 	}
-	
+
 	/* Compute the memory base address */
 	base_k = memory_end_k(ctrl, ctrl->node_id);
 	tom_k += base_k;
@@ -1303,11 +1294,10 @@ static void order_dimms(const struct mem_controller *ctrl,
 	set_top_mem(tom_k, 0);
 }
 
-
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
 			  struct mem_info *meminfo)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@ -1326,7 +1316,6 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
 	return meminfo->dimm_mask;
 }
 
-
 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
 					 struct mem_info *meminfo)
 {
@@ -1380,17 +1369,14 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
-#if 1
 	if (meminfo->is_registered) {
-		printk_debug("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_debug("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
-#endif
 	return meminfo->dimm_mask;
 }
 
-
 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 {
 	unsigned dimm_mask;
@@ -1458,7 +1444,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 	u8 common_cl;
 
 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
-#if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12
+#if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12
 	u8 mux_cap = 1;
 #else
 	u8 mux_cap = 0;
@@ -1487,7 +1473,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 		/* Abort if the chips don't support a common CAS latency. */
 		common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
 		if (!common_cl) {
-			printk_debug("No common CAS latency supported\n");
+			printk(BIOS_DEBUG, "No common CAS latency supported\n");
 			goto single_channel;
 		} else {
 			printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
@@ -1509,7 +1495,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_BurstLength32;  /*	32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
 					32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode	*/
@@ -1528,7 +1514,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 		if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
 			/* mux capable and single dimm in channelB */
 			if (mux_cap) {
-				printk_spew("Enable 64MuxMode & BurstLength32\n");
+				printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
 				dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
 				dcm |= DCM_Mode64BitMux;
 				pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
@@ -1543,7 +1529,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 	} else { /* unmatched dual dimms ? */
 		/* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
 		meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
-		printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
+		printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1624,7 +1610,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_debug("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -1865,7 +1851,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 		int latencies;
 		int latency;
 		int index;
-		int value;
+		int val;
 		u32 spd_device = ctrl->channel0[i];
 
 		if (!(meminfo->dimm_mask & (1 << i))) {
@@ -1899,14 +1885,14 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 		}
 
 		/* Read the min_cycle_time for this latency */
-		value = spd_read_byte(spd_device, latency_indicies[index]);
-		if (value < 0) goto hw_error;
+		val = spd_read_byte(spd_device, latency_indicies[index]);
+		if (val < 0) goto hw_error;
 
-		value = convert_to_linear(value);
+		val = convert_to_linear(val);
 		/* All is good if the selected clock speed
 		 * is what I need or slower.
 		 */
-		if (value <= min_cycle_time) {
+		if (val <= min_cycle_time) {
 			continue;
 		}
 		/* Otherwise I have an error, disable the dimm */
@@ -1926,7 +1912,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 	value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
 
-	printk_debug("%s\n", result.param->name);
+	printk(BIOS_DEBUG, "%s\n", result.param->name);
 
 	/* Update DRAM Timing Low with our selected cas latency */
 	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
@@ -1974,7 +1960,7 @@ int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
 
 	if (clocks < DTL_TRC_MIN) {
 #warning We should die here or at least disable this bank.
-		printk_notice("update_dimm_Trc: can't refresh fast enough, "
+		printk(BIOS_NOTICE, "update_dimm_Trc: can't refresh fast enough, "
 			"want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
 		clocks = DTL_TRC_MIN;
 	}
@@ -2071,7 +2057,8 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
 	}
 	
 	if (clocks > TT_MAX) {
-		return 0;
+		printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
+		clocks = TT_MAX;
 	}
 
 	dtl = pci_read_config32(ctrl->f2, TT_REG);
@@ -2087,7 +2074,6 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
 	return 1;
 }
 
-
 static int update_dimm_Trcd(const struct mem_controller *ctrl,
 			     const struct mem_param *param, int i, long dimm_mask)
 {
@@ -2125,17 +2111,14 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_
 	if (clocks < DTL_TRAS_MIN) {
 		clocks = DTL_TRAS_MIN;
 	}
-
 	if (clocks > DTL_TRAS_MAX) {
 		return 0;
 	}
-
 	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
 	if (old_clocks >= clocks) { // someone did it?
 		return 1;
 	}
-
 	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
 	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
 	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
@@ -2200,13 +2183,13 @@ static int update_dimm_Tref(const struct mem_controller *ctrl,
 	return 1;
 }
 
-
 static void set_4RankRDimm(const struct mem_controller *ctrl,
 			const struct mem_param *param, struct mem_info *meminfo)
 {
-#if QRANK_DIMM_SUPPRT == 1
+#if QRANK_DIMM_SUPPORT == 1
 	int value;
 	int i;
+	long dimm_mask = meminfo->dimm_mask;
 
 
 	if (!(meminfo->is_registered)) return;
@@ -2218,7 +2201,7 @@ static void set_4RankRDimm(const struct mem_controller *ctrl,
 			continue;
 		}
 
-		if (meminfo->sz.rank == 4) {
+		if (meminfo->sz[i].rank == 4) {
 			value = 1;
 			break;
 		}
@@ -2233,7 +2216,6 @@ static void set_4RankRDimm(const struct mem_controller *ctrl,
 #endif
 }
 
-
 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
 				     struct mem_info *meminfo)
 {
@@ -2351,7 +2333,7 @@ static void set_DramTerm(const struct mem_controller *ctrl,
 	}
 
 
-#if DIMM_SUPPORT == 0x0204
+#if CONFIG_DIMM_SUPPORT == 0x0204
 	odt = 0x2;		/* 150 ohms */
 #endif
 
@@ -2361,7 +2343,6 @@ static void set_DramTerm(const struct mem_controller *ctrl,
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 }
 
-
 static void set_ecc(const struct mem_controller *ctrl,
 	const struct mem_param *param, struct mem_info *meminfo)
 {
@@ -2391,7 +2372,7 @@ static void set_ecc(const struct mem_controller *ctrl,
 		if (!(meminfo->dimm_mask & (1 << i))) {
 			if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
 				spd_device = ctrl->channel1[i];
-				printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
+				printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device);
 			} else {
 				continue;
 			}
@@ -2424,7 +2405,7 @@ static void set_TT(const struct mem_controller *ctrl,
 	uint32_t reg;
 
 	if ((val < TT_MIN) || (val > TT_MAX)) {
-		printk_err(str);
+		printk(BIOS_ERR, str);
 		die(" Unknown\n");
 	}
 
@@ -2454,19 +2435,16 @@ static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param
 	set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
 }
 
-
 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
 }
 
-
 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
 }
 
-
 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
 {
 	static const uint8_t faw_1k[] = {8, 10, 13, 14};
@@ -2484,10 +2462,8 @@ static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *
 	}
 
 	set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
-
 }
 
-
 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	uint32_t dch;
@@ -2505,7 +2481,6 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
-
 static void set_SlowAccessMode(const struct mem_controller *ctrl)
 {
 	uint32_t dch;
@@ -2517,7 +2492,6 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl)
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
-
 /*
 	DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
 	DRAM_ADDR_TIMING_CTRL 04, 0x24
@@ -2526,11 +2500,13 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 {
 	uint32_t dword;
 	uint32_t dwordx;
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 	unsigned SlowAccessMode = 0;
+#endif
 
 	long dimm_mask = meminfo->dimm_mask & 0x0f;
 
-#if DIMM_SUPPORT==0x0104   /* DDR2 and REG */
+#if CONFIG_DIMM_SUPPORT==0x0104   /* DDR2 and REG */
 	/* for REG DIMM */
 	dword = 0x00111222;
 	dwordx = 0x002f0000;
@@ -2554,7 +2530,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 
 #endif
 
-#if DIMM_SUPPORT==0x0204	/* DDR2 and SO-DIMM, S1G1 */
+#if CONFIG_DIMM_SUPPORT==0x0204	/* DDR2 and SO-DIMM, S1G1 */
 	dword = 0x00111222;
 	dwordx = 0x002F2F00;
 
@@ -2594,7 +2570,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 	}
 #endif
 
-#if DIMM_SUPPORT==0x0004  /* DDR2 and unbuffered */
+#if CONFIG_DIMM_SUPPORT==0x0004  /* DDR2 and unbuffered */
 	/* for UNBUF DIMM */
 	dword = 0x00111222;
 	dwordx = 0x002f2f00;
@@ -2676,7 +2652,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 	printk_raminit("\tAddr Timing= %08x\n", dwordx);
 #endif
 
-#if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 	if (SlowAccessMode) {
 		set_SlowAccessMode(ctrl);
 	}
@@ -2707,7 +2683,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 static void set_RDqsEn(const struct mem_controller *ctrl,
 			const struct mem_param *param, struct mem_info *meminfo)
 {
-#if CPU_SOCKET_TYPE==0x10
+#if CONFIG_CPU_SOCKET_TYPE==0x10
 	//only need to set for reg and x8
 	uint32_t dch;
 
@@ -2722,7 +2698,6 @@ static void set_RDqsEn(const struct mem_controller *ctrl,
 #endif
 }
 
-
 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
 				  const struct mem_param *param)
 {
@@ -2735,14 +2710,12 @@ static void set_idle_cycle_limit(const struct mem_controller *ctrl,
 	pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
 }
 
-
 static void set_RdWrQByp(const struct mem_controller *ctrl,
 			  const struct mem_param *param)
 {
 	set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
 }
 
-
 static long spd_set_dram_timing(const struct mem_controller *ctrl,
 				 const struct mem_param *param,
 				 struct mem_info *meminfo)
@@ -2792,7 +2765,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl,
 
 		continue;
 	dimm_err:
-		printk_debug("spd_set_dram_timing dimm_err!\n");
+		printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n");
 		if (rc < 0) {
 			return -1;
 		}
@@ -2842,7 +2815,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl,
 #endif
 	meminfo = &sysinfo->meminfo[ctrl->node_id];
 
-	printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx);
+	printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", &paramx);
 
 	activate_spd_rom(ctrl);
 	meminfo->dimm_mask = spd_detect_dimms(ctrl);
@@ -2851,7 +2824,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl,
 
 	if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
 	{
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
@@ -2901,7 +2874,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl,
 
 #include "raminit_f_dqs.c"
 
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
 {
 	int ii;
@@ -2962,9 +2935,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 	uint32_t hole_startk;
 	int i;
 
-	hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
+	hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
 
-#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
+	printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 	/* We need to double check if the hole_startk is valid, if it is equal
 	   to basek, we need to decrease it some */
 	uint32_t basek_pri;
@@ -2984,6 +2958,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 			}
 			basek_pri = base_k;
 	}
+	printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
 #endif
 	/* find node index that need do set hole */
 	for (i=0; i < controllers; i++) {
@@ -3008,20 +2983,26 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 }
 #endif
 
+#include "exit_from_self.c"
 
 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 			  struct sys_info *sysinfo)
 {
 	int i;
-
+#ifdef ACPI_IS_WAKEUP_EARLY
+	int suspend = acpi_is_wakeup_early();
+#else
+	int suspend = 0;
+#endif
+ 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	 unsigned cpu_f0_f1[8];
 	/* FIXME: How about 32 node machine later? */
 	tsc_t tsc, tsc0[8];
 
-	printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
-#endif
+	printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]);
 	uint32_t dword;
+#endif
 
 	/* Error if I don't have memory */
 	if (memory_end_k(ctrl, controllers) == 0) {
@@ -3030,7 +3011,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 
 	/* Before enabling memory start the memory clocks */
 	for (i = 0; i < controllers; i++) {
-		uint32_t dtl, dch;
+		uint32_t dch;
 		if (!sysinfo->ctrl_present[ i ])
 			continue;
 		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
@@ -3050,14 +3031,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 
 	/* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
 	memreset(controllers, ctrl);
-#if 0
-	printk_debug("prepare to InitDram:");
-	for (i=0; i<10; i++) {
-		printk_debug("%08x", i);
-		print_debug("\b\b\b\b\b\b\b\b");
+
+	/* lets override the rest of the routine */
+	if (suspend) {
+		printk(BIOS_DEBUG, "Wakeup!\n");
+		exit_from_self(controllers, ctrl, sysinfo);
+		printk(BIOS_DEBUG, "Mem running !\n");
+		return;
 	}
-	printk_debug("\n");
-#endif
 
 	for (i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
@@ -3073,7 +3054,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -3096,36 +3077,29 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 		}
 #endif
 
-#if 0
-		/* Set the DqsRcvEnTrain bit */
-		dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
-		dword |= DC_DqsRcvEnTrain;
-		pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
-#endif
-
 		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 		dcl |= DCL_InitDram;
 		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 	}
 
 	for (i = 0; i < controllers; i++) {
-		uint32_t dcl, dch, dcm;
+		uint32_t dcl, dcm;
 		if (!sysinfo->ctrl_present[ i ])
 			continue;
 		/* Skip everything if I don't have any memory on this controller */
 		if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -3153,10 +3127,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 			print_debug_dqs_tsc("     dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
 		}
 #endif
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 	/* init hw mem hole here */
 	/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
 	set_hw_mem_hole(controllers, ctrl);
@@ -3188,7 +3162,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 	}
 
 
-#if MEM_TRAIN_SEQ ==  0
+#if CONFIG_MEM_TRAIN_SEQ ==  0
    #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	dqs_timing(controllers, ctrl, tsc0, sysinfo);
    #else
@@ -3196,7 +3170,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
    #endif
 #else
 
-#if MEM_TRAIN_SEQ == 2
+#if CONFIG_MEM_TRAIN_SEQ == 2
 	/* need to enable mtrr, so dqs training could access the test address  */
 	setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
 #endif
@@ -3208,26 +3182,25 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 
 		dqs_timing(i, &ctrl[i], sysinfo, 1);
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
 		break; // only train the first node with ram
 #endif
 	}
 
-#if MEM_TRAIN_SEQ == 2
+#if CONFIG_MEM_TRAIN_SEQ == 2
 	clear_mtrr_dqs(sysinfo->tom2_k);
 #endif
 
 #endif
 
-#if MEM_TRAIN_SEQ != 1
+#if CONFIG_MEM_TRAIN_SEQ != 1
 	wait_all_core0_mem_trained(sysinfo);
 #endif
 
 }
 
-
 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
-			   const uint16_t *spd_addr)
+			  const uint16_t *spd_addr)
 {
 	int i;
 	int j;