X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Famdk8%2Framinit_f.c;h=33df485c8c7b255acf4553189a2ab3937b6e39a2;hb=c5fc7db3559e080858461b724251f87be6faa2cd;hp=9ccc56b2b2b3891a3e2405e9e3ab7de4c46cd8fe;hpb=d4814bd41c080fb9dda87c762fcaecf4e72fc996;p=coreboot.git

diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 9ccc56b2b..33df485c8 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -49,7 +49,7 @@
 	/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
 	 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
 	/*
-		index:
+index:
 		[29: 0] DctOffset (Dram Controller Offset)
 		[30:30] DctAccessWrite (Dram Controller Read/Write Select)
 			0 = read access
@@ -659,7 +659,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
 	 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
 	/*
-		index:
+index:
 		[29: 0] DctOffset (Dram Controller Offset)
 		[30:30] DctAccessWrite (Dram Controller Read/Write Select)
 			0 = read access
@@ -820,7 +820,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 	sz->col = 0;
 	sz->bank = 0;
 	sz->rank = 0;
- out:
+out:
 	return;
 }
 
@@ -1108,10 +1108,10 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
 	 * and if so count them.
 	 */
 #if defined(CMOS_VSTART_interleave_chip_selects)
-	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0)
+	if (read_option(interleave_chip_selects, 1) == 0)
 		return 0;
 #else
-#if !CONFIG_INTERLEAVE_CHIP_SELECTS
+#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS
 	return 0;
 #endif
 #endif
@@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 		18,	/* *Supported CAS Latencies */
 		9,	/* *Cycle time at highest CAS Latency CL=X */
 		23,	/* *Cycle time at CAS Latency (CLX - 1) */
-		26,	/* *Cycle time at CAS Latency (CLX - 2) */
+		25,	/* *Cycle time at CAS Latency (CLX - 2) */
 	};
 	u32 dcl, dcm;
 	u8 common_cl;
@@ -1806,7 +1806,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 	bios_cycle_time = min_cycle_times[
 #ifdef CMOS_VSTART_max_mem_clock
-		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)
+		read_option(max_mem_clock, 0)
 #else
 #if defined(CONFIG_MAX_MEM_CLOCK)
 		CONFIG_MAX_MEM_CLOCK
@@ -1815,7 +1815,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 #endif
 #endif
 	];
-	
+
 	if (bios_cycle_time > min_cycle_time) {
 		min_cycle_time = bios_cycle_time;
 	}
@@ -2375,7 +2375,7 @@ static void set_ecc(const struct mem_controller *ctrl,
 		dcl |= DCL_DimmEccEn;
 	}
 #ifdef CMOS_VSTART_ECC_memory
-	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+	if (read_option(ECC_memory, 1) == 0) {
 		dcl &= ~DCL_DimmEccEn;
 	}
 #else // CMOS_VSTART_ECC_memory not defined