X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Famdk8%2Framinit_f.c;h=319293b7ed61e9f138efeb6e261d57040e8ab19e;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hp=097e3b53a53c24369c165439c66379460587861d;hpb=15bf50d8203af20b3079e6691bf0d9eee66ea1bd;p=coreboot.git diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 097e3b53a..319293b7e 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -20,39 +20,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include #include #include #include #include #include "raminit.h" -#include "amdk8_f.h" +#include "f.h" #include - -#ifndef QRANK_DIMM_SUPPORT -#define QRANK_DIMM_SUPPORT 0 -#endif - -#if CONFIG_USE_PRINTK_IN_CAR -#else -#error This file needs CONFIG_USE_PRINTK_IN_CAR +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" #endif -#define RAM_TIMING_DEBUG 0 - -#if RAM_TIMING_DEBUG == 1 -#define printk_raminit printk_debug +#if CONFIG_DEBUG_RAM_SETUP +#define printk_raminit(args...) printk(BIOS_DEBUG, args) #else -#define printk_raminit(fmt, arg...) +#define printk_raminit(args...) #endif -#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 -# error "CONFIG_LB_MEM_TOPK must be a power of 2" +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" #endif -#include "amdk8_f_pci.c" +#include "f_pci.c" /* for PCI_ADDR(0, 0x18, 2, 0x98) index, @@ -82,7 +73,7 @@ */ -static void setup_resource_map(const unsigned int *register_values, int max) +void setup_resource_map(const unsigned int *register_values, int max) { int i; for (i = 0; i < max; i += 3) { @@ -401,7 +392,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 110 = 8 bus clocks * 111 = 9 bus clocks * [ 7: 7] Reserved - * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, + * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, * minium write-to-read delay when both access the same chip select) * 00 = Reserved * 01 = 1 bus clocks @@ -533,7 +524,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * registered DIMM is present * [19:19] Reserved * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) - * 0 = DRAM address and control signals are driven for one + * 0 = DRAM address and control signals are driven for one * MEMCLK cycle * 1 = One additional MEMCLK of setup time is provided on all * DRAM address and control signals except CS, CKE, and ODT; @@ -699,7 +690,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in } sysinfo->ctrl_present[ctrl->node_id] = 1; - printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id); + printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { device_t dev; @@ -712,33 +703,34 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - - printk_spew("done.\n"); + printk(BIOS_SPEW, "done.\n"); } - +#if 0 static int is_dual_channel(const struct mem_controller *ctrl) { uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_Width128; } - +#endif static int is_opteron(const struct mem_controller *ctrl) { - /* Test to see if I am an Opteron. - * FIXME Testing dual channel capability is correct for now - * but a better test is probably required. - * m2 and s1g1 support dual channel too. but only support unbuffered dimm + /* Test to see if I am an Opteron. M2 and S1G1 support dual + * channel, too, but only support unbuffered DIMMs so we need a + * better test for Opterons. + * However, all code uses is_opteron() to find out whether to + * use dual channel, so if we really check for opteron here, we + * need to fix up all code using this function, too. */ -#warning "FIXME implement a better test for opterons" + uint32_t nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); } - +#if 0 static int is_registered(const struct mem_controller *ctrl) { /* Test to see if we are dealing with registered SDRAM. @@ -749,7 +741,7 @@ static int is_registered(const struct mem_controller *ctrl) dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBuffDimm); } - +#endif static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) { @@ -813,7 +805,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) if (value <=4 ) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines if ( value != (sz->per_rank)) { - printk_err("Bad RANK Size --\n"); + printk(BIOS_ERR, "Bad RANK Size --\n"); goto val_err; } @@ -834,7 +826,8 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) static void set_dimm_size(const struct mem_controller *ctrl, - struct dimm_size *sz, unsigned index, struct mem_info *meminfo) + struct dimm_size *sz, unsigned index, + struct mem_info *meminfo) { uint32_t base0, base1; @@ -873,7 +866,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, /* Set the appropriate DIMM base address register */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1); -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1); @@ -885,11 +878,11 @@ static void set_dimm_size(const struct mem_controller *ctrl, if (base0) { uint32_t dword; uint32_t ClkDis0; -#if CPU_SOCKET_TYPE == 0x10 /* L1 */ +#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */ ClkDis0 = DTL_MemClkDis0; -#elif CPU_SOCKET_TYPE == 0x11 /* AM2 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */ ClkDis0 = DTL_MemClkDis0_AM2; -#elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */ ClkDis0 = DTL_MemClkDis0_S1g1; #endif @@ -901,7 +894,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, } else { dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A dword &= ~(ClkDis0 >> index); -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { dword &= ~(ClkDis0 >> (index+2)); } @@ -911,7 +904,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, if (meminfo->is_Width128) { // ChannelA+B dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); dword &= ~(ClkDis0 >> index); -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { dword &= ~(ClkDis0 >> (index+2)); } @@ -964,7 +957,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, } map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { map &= ~(0xf << ( (index + 2) * 4)); } @@ -975,7 +968,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, unsigned temp_map; temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ]; map |= temp_map << (index*4); -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { map |= temp_map << ( (index + 2) * 4); } @@ -1009,14 +1002,13 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, return -1; /* Report SPD error */ } set_dimm_size(ctrl, sz, i, meminfo); - set_dimm_cs_map (ctrl, sz, i, meminfo); + set_dimm_cs_map(ctrl, sz, i, meminfo); } return meminfo->dimm_mask; } - static void route_dram_accesses(const struct mem_controller *ctrl, - unsigned long base_k, unsigned long limit_k) + unsigned long base_k, unsigned long limit_k) { /* Route the addresses to the controller node */ unsigned node_id; @@ -1045,7 +1037,6 @@ static void route_dram_accesses(const struct mem_controller *ctrl, } } - static void set_top_mem(unsigned tom_k, unsigned hole_startk) { /* Error if I don't have memory */ @@ -1054,27 +1045,32 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Report the amount of memory. */ - printk_debug("RAM: 0x%08x kB\n", tom_k); + printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k); + /* Now set top of memory */ msr_t msr; if (tom_k > (4*1024*1024)) { - /* Now set top of memory */ + printk_raminit("Handling memory mapped above 4 GB\n"); + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); + printk_raminit("Correcting memory amount mapped below 4 GB\n"); } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else #endif tom_k = 0x3f0000; + printk_raminit("Adjusting lower RAM end\n"); } + printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); @@ -1111,6 +1107,15 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, /* See if all of the memory chip selects are the same size * and if so count them. */ +#if defined(CMOS_VSTART_interleave_chip_selects) + if (read_option(interleave_chip_selects, 1) == 0) + return 0; +#else +#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS + return 0; +#endif +#endif + chip_selects = 0; common_size = 0; common_cs_mode = 0xff; @@ -1161,7 +1166,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, csbase_inc <<=1; } - /* Compute the initial values for csbase and csbask. * In csbase just set the enable bit and the base to zero. * In csmask set the mask bits for the size and page level interleave. @@ -1184,11 +1188,12 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, csbase += csbase_inc; } - printk_debug("Interleaved\n"); + printk(BIOS_DEBUG, "Interleaved\n"); /* Return the memory size in K */ return common_size << ((27-10) + bits); } + static unsigned long order_chip_selects(const struct mem_controller *ctrl) { unsigned long tom; @@ -1224,7 +1229,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) csbase = value; canidate = index; } - + /* See if I have found a new canidate */ if (csbase == 0) { break; @@ -1258,7 +1263,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) return (tom & ~0xff000000) << (27-10); } -unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id) +static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id) { unsigned node_id; unsigned end_k; @@ -1278,24 +1283,18 @@ unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id) return end_k; } - static void order_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo) { unsigned long tom_k, base_k; - if (read_option(CMOS_VSTART_interleave_chip_selects, - CMOS_VLEN_interleave_chip_selects, 1) != 0) { - tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); - } else { - printk_debug("Interleaving disabled\n"); - tom_k = 0; - } - + tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); + if (!tom_k) { + printk(BIOS_DEBUG, "Interleaving disabled\n"); tom_k = order_chip_selects(ctrl); } - + /* Compute the memory base address */ base_k = memory_end_k(ctrl, ctrl->node_id); tom_k += base_k; @@ -1303,18 +1302,17 @@ static void order_dimms(const struct mem_controller *ctrl, set_top_mem(tom_k, 0); } - static long disable_dimm(const struct mem_controller *ctrl, unsigned index, struct mem_info *meminfo) { - printk_debug("disabling dimm %02x\n", index); + printk(BIOS_DEBUG, "disabling dimm %02x\n", index); if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); } else { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0); -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT if (meminfo->sz[index].rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); @@ -1326,7 +1324,6 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, return meminfo->dimm_mask; } - static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo) { @@ -1380,17 +1377,14 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); -#if 1 if (meminfo->is_registered) { - printk_debug("Registered\n"); + printk(BIOS_SPEW, "Registered\n"); } else { - printk_debug("Unbuffered\n"); + printk(BIOS_SPEW, "Unbuffered\n"); } -#endif return meminfo->dimm_mask; } - static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) { unsigned dimm_mask; @@ -1458,7 +1452,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ -#if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 +#if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12 u8 mux_cap = 1; #else u8 mux_cap = 0; @@ -1487,7 +1481,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i /* Abort if the chips don't support a common CAS latency. */ common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18); if (!common_cl) { - printk_debug("No common CAS latency supported\n"); + printk(BIOS_DEBUG, "No common CAS latency supported\n"); goto single_channel; } else { printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl); @@ -1509,7 +1503,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i } } } - printk_spew("Enabling dual channel memory\n"); + printk(BIOS_SPEW, "Enabling dual channel memory\n"); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */ @@ -1528,7 +1522,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { /* mux capable and single dimm in channelB */ if (mux_cap) { - printk_spew("Enable 64MuxMode & BurstLength32\n"); + printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n"); dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); dcm |= DCM_Mode64BitMux; pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm); @@ -1543,7 +1537,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i } else { /* unmatched dual dimms ? */ /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */ meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS)); - printk_spew("Unmatched dual dimms. Use single channelA dimm.\n"); + printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n"); } return meminfo->dimm_mask; } @@ -1624,7 +1618,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) if (!param->cycle_time) { die("min_cycle_time to low"); } - printk_debug("%s\n", param->name); + printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1649,7 +1643,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) /*15*/ 200, 160, 120, 100, }; - + int index; msr_t msr; @@ -1668,7 +1662,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) unsigned fid_start; msr = rdmsr(0xc0010015); fid_start = (msr.lo & (0x3f << 24)); - + index = fid_start>>25; } @@ -1704,7 +1698,7 @@ static unsigned convert_to_linear(unsigned value) static const uint8_t latency_indicies[] = { 25, 23, 9 }; -int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) +static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) { int new_cycle_time, new_latency; int index; @@ -1811,7 +1805,17 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ - read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; +#ifdef CMOS_VSTART_max_mem_clock + read_option(max_mem_clock, 0) +#else +#if defined(CONFIG_MAX_MEM_CLOCK) + CONFIG_MAX_MEM_CLOCK +#else + 0 // use DDR400 as default +#endif +#endif + ]; + if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } @@ -1852,7 +1856,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * continue; } } - + } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. @@ -1865,7 +1869,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * int latencies; int latency; int index; - int value; + int val; u32 spd_device = ctrl->channel0[i]; if (!(meminfo->dimm_mask & (1 << i))) { @@ -1899,14 +1903,14 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * } /* Read the min_cycle_time for this latency */ - value = spd_read_byte(spd_device, latency_indicies[index]); - if (value < 0) goto hw_error; + val = spd_read_byte(spd_device, latency_indicies[index]); + if (val < 0) goto hw_error; - value = convert_to_linear(value); + val = convert_to_linear(val); /* All is good if the selected clock speed * is what I need or slower. */ - if (value <= min_cycle_time) { + if (val <= min_cycle_time) { continue; } /* Otherwise I have an error, disable the dimm */ @@ -1926,7 +1930,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); - printk_debug("%s\n", result.param->name); + printk(BIOS_DEBUG, "%s\n", result.param->name); /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); @@ -1952,7 +1956,7 @@ static unsigned convert_to_1_4(unsigned value) return valuex; } -int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param) +static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param) { int value; int value2; @@ -1973,9 +1977,9 @@ int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param) printk_raminit("update_dimm_Trc: clocks = %i\n", clocks); if (clocks < DTL_TRC_MIN) { -#warning We should die here or at least disable this bank. - printk_notice("update_dimm_Trc: can't refresh fast enough, " - "want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN); + // We might want to die here instead or (at least|better) disable this bank. + printk(BIOS_NOTICE, "update_dimm_Trc: Can't refresh fast enough, " + "want %i clocks, minimum is %i clocks.\n", clocks, DTL_TRC_MIN); clocks = DTL_TRC_MIN; } return clocks; @@ -2069,9 +2073,9 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me if (clocks < TT_MIN) { clocks = TT_MIN; } - + if (clocks > TT_MAX) { - printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX); + printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX); clocks = TT_MAX; } @@ -2088,7 +2092,6 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me return 1; } - static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask) { @@ -2126,17 +2129,14 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_ if (clocks < DTL_TRAS_MIN) { clocks = DTL_TRAS_MIN; } - if (clocks > DTL_TRAS_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE; if (old_clocks >= clocks) { // someone did it? return 1; } - dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT); dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT); pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); @@ -2201,13 +2201,13 @@ static int update_dimm_Tref(const struct mem_controller *ctrl, return 1; } - static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if QRANK_DIMM_SUPPRT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT int value; int i; + long dimm_mask = meminfo->dimm_mask; if (!(meminfo->is_registered)) return; @@ -2219,7 +2219,7 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, continue; } - if (meminfo->sz.rank == 4) { + if (meminfo->sz[i].rank == 4) { value = 1; break; } @@ -2234,7 +2234,6 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, #endif } - static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, struct mem_info *meminfo) { @@ -2245,7 +2244,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, uint32_t mask_single_rank; uint32_t mask_page_1k; int value; -#if QRANK_DIMM_SUPPORT == 1 +#if CONFIG_QRANK_DIMM_SUPPORT int rank; #endif @@ -2278,20 +2277,20 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, value = spd_read_byte(spd_device, SPD_PRI_WIDTH); - #if QRANK_DIMM_SUPPORT == 1 + #if CONFIG_QRANK_DIMM_SUPPORT rank = meminfo->sz[i].rank; #endif if (value==4) { mask_x4 |= (1<f2, DRAM_CONFIG_LOW, dcl); } - static void set_ecc(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { @@ -2376,14 +2374,21 @@ static void set_ecc(const struct mem_controller *ctrl, if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { +#ifdef CMOS_VSTART_ECC_memory + if (read_option(ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } +#else // CMOS_VSTART_ECC_memory not defined +#if !CONFIG_ECC_MEMORY + dcl &= ~DCL_DimmEccEn; +#endif +#endif pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); meminfo->is_ecc = 1; if (!(dcl & DCL_DimmEccEn)) { meminfo->is_ecc = 0; + printk(BIOS_DEBUG, "set_ecc: ECC disabled\n"); return; // already disabled the ECC, so don't need to read SPD any more } @@ -2392,7 +2397,7 @@ static void set_ecc(const struct mem_controller *ctrl, if (!(meminfo->dimm_mask & (1 << i))) { if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */ spd_device = ctrl->channel1[i]; - printk_debug("set_ecc spd_device: 0x%x\n", spd_device); + printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device); } else { continue; } @@ -2425,7 +2430,7 @@ static void set_TT(const struct mem_controller *ctrl, uint32_t reg; if ((val < TT_MIN) || (val > TT_MAX)) { - printk_err(str); + printk(BIOS_ERR, "%s", str); die(" Unknown\n"); } @@ -2455,19 +2460,16 @@ static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr"); } - static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param) { set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd"); } - static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param) { set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS } - static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { static const uint8_t faw_1k[] = {8, 10, 13, 14}; @@ -2485,10 +2487,8 @@ static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param * } set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow"); - } - static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) { uint32_t dch; @@ -2506,7 +2506,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } - +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2517,7 +2517,7 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl) pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } - +#endif /* DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20 @@ -2527,11 +2527,12 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * { uint32_t dword; uint32_t dwordx; +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ unsigned SlowAccessMode = 0; +#endif +#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ long dimm_mask = meminfo->dimm_mask & 0x0f; - -#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; @@ -2555,7 +2556,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * #endif -#if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00; @@ -2595,7 +2596,8 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif -#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ + long dimm_mask = meminfo->dimm_mask & 0x0f; /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; @@ -2677,7 +2679,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif -#if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ if (SlowAccessMode) { set_SlowAccessMode(ctrl); } @@ -2708,7 +2710,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE==0x10 //only need to set for reg and x8 uint32_t dch; @@ -2723,7 +2725,6 @@ static void set_RDqsEn(const struct mem_controller *ctrl, #endif } - static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { @@ -2736,14 +2737,12 @@ static void set_idle_cycle_limit(const struct mem_controller *ctrl, pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm); } - static void set_RdWrQByp(const struct mem_controller *ctrl, const struct mem_param *param) { set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp"); } - static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) @@ -2793,7 +2792,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, continue; dimm_err: - printk_debug("spd_set_dram_timing dimm_err!\n"); + printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n"); if (rc < 0) { return -1; } @@ -2843,7 +2842,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, #endif meminfo = &sysinfo->meminfo[ctrl->node_id]; - printk_debug("sdram_set_spd_registers: paramx :%p\n", ¶mx); + printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", ¶mx); activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl); @@ -2852,7 +2851,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { - printk_debug("No memory for this cpu\n"); + printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); @@ -2902,7 +2901,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, #include "raminit_f_dqs.c" -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2963,9 +2962,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; @@ -2985,6 +2985,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) } basek_pri = base_k; } + printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* find node index that need do set hole */ for (i=0; i < controllers; i++) { @@ -3008,27 +3009,28 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) } #endif - +#if CONFIG_HAVE_ACPI_RESUME == 1 #include "exit_from_self.c" +#endif static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; -#ifdef ACPI_IS_WAKEUP_EARLY +#if CONFIG_HAVE_ACPI_RESUME == 1 int suspend = acpi_is_wakeup_early(); #else int suspend = 0; #endif - + #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 unsigned cpu_f0_f1[8]; /* FIXME: How about 32 node machine later? */ tsc_t tsc, tsc0[8]; - printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]); -#endif + printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]); uint32_t dword; +#endif /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { @@ -3037,7 +3039,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, /* Before enabling memory start the memory clocks */ for (i = 0; i < controllers; i++) { - uint32_t dtl, dch; + uint32_t dch; if (!sysinfo->ctrl_present[ i ]) continue; dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); @@ -3057,20 +3059,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */ memreset(controllers, ctrl); -#if 0 - printk_debug("prepare to InitDram:"); - for (i=0; i<10; i++) { - printk_debug("%08x", i); - print_debug("\b\b\b\b\b\b\b\b"); - } - printk_debug("\n"); -#endif /* lets override the rest of the routine */ if (suspend) { - printk_debug("Wakeup!\n"); + printk(BIOS_DEBUG, "Wakeup!\n"); exit_from_self(controllers, ctrl, sysinfo); - printk_debug("Mem running !\n"); + printk(BIOS_DEBUG, "Mem running !\n"); return; } @@ -3088,7 +3082,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { uint32_t mnc; - printk_spew("ECC enabled\n"); + printk(BIOS_SPEW, "ECC enabled\n"); mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_Width128) { @@ -3111,36 +3105,29 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } #endif -#if 0 - /* Set the DqsRcvEnTrain bit */ - dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); - dword |= DC_DqsRcvEnTrain; - pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword); -#endif - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); dcl |= DCL_InitDram; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); } for (i = 0; i < controllers; i++) { - uint32_t dcl, dch, dcm; + uint32_t dcl, dcm; if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ if (sysinfo->meminfo[i].dimm_mask==0x00) continue; - printk_debug("Initializing memory: "); + printk(BIOS_DEBUG, "Initializing memory: "); int loops = 0; do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops++; if ((loops & 1023) == 0) { - printk_debug("."); + printk(BIOS_DEBUG, "."); } } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { - printk_debug(" failed\n"); + printk(BIOS_DEBUG, " failed\n"); continue; } @@ -3168,10 +3155,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2); } #endif - printk_debug(" done\n"); + printk(BIOS_DEBUG, " done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); @@ -3203,7 +3190,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 dqs_timing(controllers, ctrl, tsc0, sysinfo); #else @@ -3211,7 +3198,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, #endif #else -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 /* need to enable mtrr, so dqs training could access the test address */ setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -3223,26 +3210,25 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dqs_timing(i, &ctrl[i], sysinfo, 1); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 break; // only train the first node with ram #endif } -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 clear_mtrr_dqs(sysinfo->tom2_k); #endif #endif -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 wait_all_core0_mem_trained(sysinfo); #endif } - -static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, - const uint16_t *spd_addr) +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, + const uint16_t *spd_addr) { int i; int j;