X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Famdk8%2Fcoherent_ht.c;h=a262686f871609d5643c479c92775f1730a33e90;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hp=d24a83c68f86981286d2a59b4c093af37d975892;hpb=678d6140a5f75bde7b5a6b7ef296ebb7a3dda166;p=coreboot.git diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index d24a83c68..a262686f8 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -68,6 +68,10 @@ #include #include #include "arch/romcc_io.h" +#include +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #include "amdk8.h" @@ -88,8 +92,8 @@ #define TRY_HIGH_FIRST 0 #endif -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef K8_HT_CHECK_PENDING_LINK @@ -104,20 +108,14 @@ #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 #endif -#ifndef ENABLE_APIC_EXT_ID - #define ENABLE_APIC_EXT_ID 0 +#ifndef CONFIG_ENABLE_APIC_EXT_ID + #define CONFIG_ENABLE_APIC_EXT_ID 0 #endif static inline void print_linkn (const char *strval, uint8_t byteval) { -#if 1 -#if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%s%02x\r\n", strval, byteval); -#else - print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n"); -#endif -#endif + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static void disable_probes(void) @@ -155,13 +153,14 @@ static void disable_probes(void) HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); - print_spew("done.\r\n"); + print_spew("done.\n"); } +#if 0 static void enable_apic_ext_id(u8 node) { -#if ENABLE_APIC_EXT_ID==1 +#if CONFIG_ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?" u32 val; @@ -171,6 +170,7 @@ static void enable_apic_ext_id(u8 node) pci_write_config32(NODE_HT(node), 0x68, val); #endif } +#endif static void enable_routing(u8 node) { @@ -206,15 +206,15 @@ static void enable_routing(u8 node) val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } +#if CONFIG_MAX_PHYSICAL_CPUS > 1 static void fill_row(u8 node, u8 row, u32 value) { pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); } -#if CONFIG_MAX_PHYSICAL_CPUS > 1 static u8 link_to_register(int ldt) { /* @@ -256,7 +256,7 @@ static void rename_temp_node(u8 node) val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static int verify_connection(u8 dest) @@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) #endif { @@ -384,6 +384,7 @@ static uint8_t get_linkn_first(uint8_t byte) return byte; } +#if TRY_HIGH_FIRST == 1 static uint8_t get_linkn_last(uint8_t byte) { if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } @@ -391,7 +392,9 @@ static uint8_t get_linkn_last(uint8_t byte) if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } return byte>>4; } +#endif +#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) static uint8_t get_linkn_last_count(uint8_t byte) { byte &= 0x0f; @@ -400,6 +403,7 @@ static uint8_t get_linkn_last_count(uint8_t byte) if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } return byte>>4; } +#endif static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/ { @@ -446,28 +450,33 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) } #if CROSS_BAR_47_56 -static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) { +static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) +{ uint32_t val; val = get_row(source, dest); val -= link_connection(source, kickout)<<16; fill_row(source, dest, val); } -static void opt_broadcast_rt_group(const u8 *conn, int num) { +static void opt_broadcast_rt_group(const u8 *conn, int num) +{ int i; for(i=0; i 1*/ @@ -658,7 +664,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) static void setup_uniprocessor(void) { - print_spew("Enabling UP settings\r\n"); + print_spew("Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS==1 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; @@ -667,7 +673,8 @@ static void setup_uniprocessor(void) } #if CONFIG_MAX_PHYSICAL_CPUS > 2 -static int optimize_connection_group(const u8 *opt_conn, int num) { +static int optimize_connection_group(const u8 *opt_conn, int num) +{ int needs_reset = 0; int i; for(i=0; i 2 @@ -1502,12 +1509,7 @@ static unsigned setup_smp(void) nodes = setup_smp8(); #endif -#if CONFIG_USE_PRINTK_IN_CAR - printk_debug("%02x nodes initialized.\r\n", nodes); -#else - print_debug_hex8(nodes); - print_debug(" nodes initialized.\r\n"); -#endif + printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes); return nodes; } @@ -1526,14 +1528,14 @@ static unsigned verify_mp_capabilities(unsigned nodes) #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ if(nodes > 2) { - print_err("Going back to DP\r\n"); + print_err("Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ if(nodes >1 ) { - print_err("Going back to UP\r\n"); + print_err("Going back to UP\n"); return 1; } break; @@ -1591,14 +1593,13 @@ static unsigned verify_dualcore(unsigned nodes) static void coherent_ht_finalize(unsigned nodes) { unsigned node; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 int rev_a0; #endif #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if ((!HAVE_OPTION_TABLE) || - read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ + if (read_option(multi_core, 0) == 0) { /* multi_core */ total_cpus = verify_dualcore(nodes); } else { @@ -1612,8 +1613,8 @@ static void coherent_ht_finalize(unsigned nodes) * registers on Hammer A0 revision. */ - print_spew("coherent_ht_finalize\r\n"); -#if K8_REV_F_SUPPORT == 0 + print_spew("coherent_ht_finalize\n"); +#if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { @@ -1644,7 +1645,7 @@ static void coherent_ht_finalize(unsigned nodes) (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); @@ -1653,7 +1654,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif } - print_spew("done\r\n"); + print_spew("done\n"); } static int apply_cpu_errata_fixes(unsigned nodes) @@ -1664,7 +1665,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) device_t dev; uint32_t cmd; dev = NODE_MC(node); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 66 @@ -1707,6 +1708,21 @@ static int apply_cpu_errata_fixes(unsigned nodes) } } #endif + + +#if CONFIG_K8_REV_F_SUPPORT == 0 + /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */ + if (!is_cpu_pre_b3()) +#endif + { + /* Errata 169 */ + /* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */ + dev = NODE_HT(node); + cmd = pci_read_config32(dev, 0x68); + cmd &= ~(1 << 22); + cmd |= (1 << 21); + pci_write_config32(dev, 0x68, cmd); + } } return needs_reset; } @@ -1812,7 +1828,7 @@ static int optimize_link_coherent_ht(void) return needs_reset; } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void setup_coherent_ht_domain(void) #else static int setup_coherent_ht_domain(void) @@ -1834,7 +1850,7 @@ static int setup_coherent_ht_domain(void) } coherent_ht_finalize(nodes); -#if RAMINIT_SYSINFO == 0 +#if !CONFIG_RAMINIT_SYSINFO return optimize_link_coherent_ht(); #endif }