X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Famdht%2FAsPsDefs.h;h=ccee1fdff03c7e468d219af9a82f3e64fb0aa854;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hp=3907208290dc04c3a3508a699e39e7eaac31f657;hpb=1f93fea160fff042f7d5467c56eaf2fc0286995f;p=coreboot.git

diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 390720829..ccee1fdff 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -25,7 +25,7 @@
 #define APIC_BAR_BP 0x100		/* APIC_BAR BSP bit */
 
 #define PS_LIM_REG 0xC0010061		/* P-state Current Limit Register */
-#define PS_CUR_LIM_SHFT 4		/* P-state Current Limit shift position */
+#define PS_MAX_VAL_SHFT 4		/* P-state Maximum Value shift position */
 
 #define PS_CTL_REG 0xC0010062		/* P-state Control Register */
 #define PS_CMD_MASK_OFF 0xfffffff8	/* P-state Control Register CMD Mask OFF */
@@ -44,6 +44,10 @@
 #define PS_REG3 3			/* offset for P3 */
 #define PS_REG4 4			/* offset for P4 */
 
+#define PS_IDD_VALUE_SHFT 0            /* IddValue: current value
+					  field offset for msr.hi */
+#define PS_IDD_VALUE_MASK 0xFF         /* IddValue: current value
+					  field mask for msr.hi */
 #define PS_PSDIS_MASK	0x7fffffff	/* disable P-state register */
 #define PS_EN_MASK  0x80000000		/* P-state register enable mask */
 #define PS_NB_DID_MASK 0x400000	/* P-state Reg[NbDid] Mask */
@@ -54,9 +58,10 @@
 #define PS_NB_VID_SHFT 25		/* P-state bit shift for NbVid */
 #define PS_BOTH_VID_OFF 0x01ff01ff	/* Mask NbVid & CpuVid */
 #define PS_CPU_NB_VID_SHFT 16		/* P-state bit shift from CpuVid to NbVid */
-#define PS_NB_VID_SHFT 25		/* P-state NBVID shift */
 #define PS_DIS 0x7fffffff		/* disable P-state reg */
 #define PS_EN 0x80000000		/* enable P-state reg */
+#define PS_CPU_FID_MASK 0x03f           /* MSRC001_00[68:64][CpuFid]
+					   Core Frequency Id */
 #define PS_CURDIV_SHFT 8		/* P-state Current Divisor shift position */
 #define PS_CPUDID_SHIFT 6		/* P-state CPU DID shift position */
 
@@ -105,7 +110,7 @@
 #define STC_PS_LMT_MASK 0x8fffffff	/* StcPstateLimit mask off */
 
 #define CPTC0 0x0d4			/* Clock Power/Timing Control0 Register*/
-#define CPTC0_MASK 0x000c0fff		/* Reset mask for this register */
+#define CPTC0_MASK 0x000cffff		/* Reset mask for this register */
 #define CPTC0_NBFID_MASK 0xffffffe0	/* NbFid mask off for this register */
 #define CPTC0_NBFID_MON 0x1f		/* NbFid mask on for this register */
 #define NB_FID_EN 0x20			/* NbFidEn bit ON */
@@ -149,6 +154,8 @@
 #define PS_2 0x00020000		/* P-state 2 */
 #define PS_CPU_DID_1 0x40		/* Cpu Did 1 */
 
+#define NB_VID1_MASK  0x00003f80      /* F3x1F4[NbVid1]*/
+#define NB_VID1_SHIFT  7      /* F3x1F4[NbVid1] */
 
 
 
@@ -185,6 +192,7 @@
 #define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS)  /* NbsynPtrAdj bit mask */
 
 #define PRCT_INFO 0x1fc		/* Product Info Register */
+#define DUAL_PLANE_ONLY_MASK 0x80000000  /* F3x1FC[DualPlaneOnly] */
 #define UNI_NB_FID_BIT 2		/* UniNbFid bit position */
 #define UNI_NB_VID_BIT 7		/* UniNbVid bit position */
 #define SPLT_NB_FID_OFFSET 14		/* SpltNbFidOffset value bit position */
@@ -193,6 +201,10 @@
 #define NB_VID_UPDATE_ALL 0x02		/* F3x1FC[NbVidUpdatedAll] bit mask */
 #define C_FID_DID_M_OFF  0xfffffe00	/* mask off Core FID & DID */
 
+#define CPB_MASK 0x00000020             /* core performance
+					   boost. CPUID Fn8000 0007 edx */
+#define NC_MASK 0x000000FF              /* number of cores - 1. CPUID
+					   Fn8000 0008 ecx */
 #define PW_CTL_MISC 0x0a0		/* Power Control Miscellaneous Register */
 #define COF_VID_PROG_BIT 0x80000000	/* CofVidProg bit. 0= unfused part */
 #define DUAL_VDD_BIT 0x40000000	/* DualVdd bit. */
@@ -229,6 +241,18 @@
 /* F3x1F0 Product Information Register */
 #define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */
 
+/* F3x1FC Product Information Register */
+#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */
+#define SINGLE_PLANE_NB_FID_MASK 0x007c/* for CPU rev <= C */
+#define SINGLE_PLANE_NB_FID_SHIFT 2/* for CPU rev <= C */
+#define SINGLE_PLANE_NB_VID_MASK 0x3f80/* for CPU rev <= C */
+#define SINGLE_PLANE_NB_VID_SHIFT 7/* for CPU rev <= C */
+
+#define DUAL_PLANE_NB_FID_OFF_MASK 0x001c000/* for CPU rev <= C */
+#define DUAL_PLANE_NB_FID_SHIFT 14/* for CPU rev <= C */
+#define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */
+#define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */
+
 
 #define NM_PS_REG 5			/* number of P-state MSR registers */
 
@@ -264,4 +288,12 @@
 #define GH_REV_A2 0x4			/* GH Rev A2 logical ID, Upper half */
 
 
+#define TSC_MSR 0x10
+#define CUR_PSTATE_MSR 0xc0010063
+#define TSC_FREQ_SEL_SHIFT 24
+
+#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
+
+#define  WAIT_PSTATE_TIMEOUT 80000000  /* 0.1 s , unit : 1.25 ns */
+
 #endif