X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Famd%2Famdfam10%2Fnorthbridge.c;h=018b6c83b0d8e81dc3be08340885918f266e1b5b;hb=2143d3737553b293923ad566ef4cda3aec742f75;hp=727a5ba10c295dd91a827de47ee936c308b2f348;hpb=687b3ba327a703e9951c1297fa49aefce0ea5655;p=coreboot.git diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 727a5ba10..018b6c83b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -47,6 +47,11 @@ #endif #include +#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 +#include +#elif CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 +#include +#endif struct amdfam10_sysconf_t sysconf; @@ -124,7 +129,7 @@ static u32 amdfam10_nodeid(device_t dev) #endif } -#include "amdfam10_conf.c" +#include "conf.c" static void set_vga_enable_reg(u32 nodeid, u32 linkn) { @@ -545,13 +550,9 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, } /** - * * I tried to reuse the resource allocation code in amdfam10_set_resource() - * but it is too diffcult to deal with the resource allocation magic. + * but it is too difficult to deal with the resource allocation magic. */ -#if CONFIG_CONSOLE_VGA_MULTI == 1 -extern device_t vga_pri; // the primary vga device, defined in device.c -#endif static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) { @@ -561,7 +562,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -687,35 +689,16 @@ static void amdfam10_domain_read_resources(device_t dev) resource->flags = IORESOURCE_MEM; } #endif +#if CONFIG_MMCONF_SUPPORT + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif } -static void ram_resource(device_t dev, unsigned long index, - resource_t basek, resource_t sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = basek << 10; - resource->size = sizek << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus, u32 tolm) +static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) { struct resource *min; min = 0; @@ -863,11 +846,23 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #endif #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include +#endif + #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; -#endif + +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} #endif static void amdfam10_domain_set_resources(device_t dev) @@ -938,7 +933,7 @@ static void amdfam10_domain_set_resources(device_t dev) pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link, pci_tolm); + pci_tolm = my_find_pci_tolm(link, pci_tolm); } // FIXME handle interleaved nodes. If you fix this here, please fix @@ -1042,13 +1037,13 @@ static void amdfam10_domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_MEMORY_SIZE / 1024, high_tables_base); } #endif } @@ -1073,6 +1068,12 @@ static void amdfam10_domain_set_resources(device_t dev) sizek -= (4*1024*1024 - mmio_basek); } } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; #if CONFIG_WRITE_HIGH_TABLES==1 @@ -1081,15 +1082,19 @@ static void amdfam10_domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + for(link = dev->link_list; link; link = link->next) { if (link->children) { assign_resources(link); @@ -1445,6 +1450,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); +#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 || CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 + sb_After_Pci_Init(); + sb_Mid_Post_Init(); +#endif } static void cpu_bus_noop(device_t dev) @@ -1453,13 +1462,6 @@ static void cpu_bus_noop(device_t dev) static void cpu_bus_read_resources(device_t dev) { -#if CONFIG_MMCONF_SUPPORT - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void cpu_bus_set_resources(device_t dev)