X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fvia%2Fepia-n%2Fromstage.c;h=30ea0f2a3a253d6f0376adb221ed040ced571955;hb=0d5a6accc84530d44f35ba4f3a74b370a1f88f86;hp=c98a663c61172738879ae550c6f90e3898ab6e28;hpb=5e32823a68f74618845c21600c8fa491f9c6c1a4;p=coreboot.git

diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index c98a663c6..30ea0f2a3 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -29,9 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "northbridge/via/cn400/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
@@ -40,13 +35,10 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
-/*
- * NOOB ::			
- * d0f0 - Device 0 Function 0 etc. 
- */
 static const struct mem_controller ctrl = {
 	.d0f0 = 0x0000,
 	.d0f2 = 0x2000,
@@ -54,14 +46,9 @@ static const struct mem_controller ctrl = {
 	.d0f4 = 0x4000,
 	.d0f7 = 0x7000,
 	.d1f0 = 0x8000,
-	.channel0 = { 0x50 },
+	.channel0 = { DIMM0 },
 };
 
-
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -73,8 +60,9 @@ static void enable_mainboard_devices(void)
 {
 	device_t dev;
 	u8 reg;
- 
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 	if (dev == PCI_DEV_INVALID)
 		die("Southbridge not found!!!\n");
 
@@ -103,10 +91,10 @@ static void enable_mainboard_devices(void)
 	pci_write_config8(dev, 0x51, 0x9d);
 }
 
-static void enable_shadow_ram(void) 
+static void enable_shadow_ram(void)
 {
 	unsigned char shadowreg;
-	
+
 	shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
 	/* 0xf0000-0xfffff Read/Write*/
 	shadowreg |= 0x30;
@@ -122,39 +110,27 @@ static void main(unsigned long bist)
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
 	w83697hf_set_clksel_48(SERIAL_DEV);
-
 	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
 	uart_init();
 	console_init();
 
-	print_spew("In romstage.c:main()\r\n");
-
 	enable_smbus();
 	smbus_fixup(&ctrl);
 
 	/* Halt if there was a built-in self test failure. */
 	report_bist_failure(bist);
 
-	print_debug("Enabling mainboard devices\r\n");
+	print_debug("Enabling mainboard devices\n");
 	enable_mainboard_devices();
 
-	print_debug("Enable F-ROM Shadow RAM\r\n");
+	print_debug("Enable F-ROM Shadow RAM\n");
 	enable_shadow_ram();
-	
-	/* setup cpu */
-	print_debug("Setup CPU Interface\r\n");
-	c3_cpu_setup(ctrl.d0f2);	
 
+	print_debug("Setup CPU Interface\n");
+	c3_cpu_setup(ctrl.d0f2);
 
 	ddr_ram_setup();
 
-	if (bist == 0) {
-		print_debug("doing early_mtrr\r\n");
+	if (bist == 0)
 		early_mtrr_init();
-	}
-	
-	//ram_check(0, 640 * 1024);
-
-	print_spew("Leaving romstage.c:main()\r\n");
 }