X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fvia%2Fepia-m700%2Fromstage.c;h=62ea809b477e687c74bf0969ca5ec9192dbf0d1f;hb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;hp=6f8a1c09dafcd222b1f4cfd193d9815d85d03de5;hpb=314e551447f408300e56cd6206af3e52d9b22059;p=coreboot.git diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 6f8a1c09d..62ea809b4 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -22,8 +22,7 @@ * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch. */ -#define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 +#define PAYLOAD_IS_SEABIOS 0 #include #include @@ -32,24 +31,18 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" -#include "lib/ramtest.c" +#include +#include #include "northbridge/via/vx800/vx800.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" #include - /* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" - #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" - #include "wakeup.h" - #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) @@ -58,7 +51,7 @@ * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. */ -int acpi_is_wakeup_early_via_vx800(void) +static int acpi_is_wakeup_early_via_vx800(void) { device_t dev; u16 tmp, result; @@ -85,17 +78,10 @@ int acpi_is_wakeup_early_via_vx800(void) return result; } -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { device_t dev; - uint16_t values; - #if 0 /* * Add and close this switch, since some line cause error, some @@ -145,6 +131,8 @@ static void enable_mainboard_devices(void) #if 0 dev = 0; dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0); + + uint16_t values; values = pci_read_config16(dev, 0xBA); values &= ~0xffff; values |= 0x5324; @@ -202,68 +190,68 @@ static void enable_shadow_ram(void) */ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { /* VT3409 no PCI-E */ - 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range - 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control + { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range + { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie + // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control // Set ROMSIP value by software /* - 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit - 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 - 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 - 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB - 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD - 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) - 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) - 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) + { 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl + { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl + { 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit + { 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status + { 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset + { 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset + { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status + { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status + { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group + { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group + { 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group + { 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1 + { 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2 + { 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB + { 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD + { 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0) + { 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1) + { 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2) + { 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3) */ // CPU Host Bus Control - 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy - 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer - 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 - 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 + { 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 }, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 + // { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + { 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB }, // CPU I/F Ctrl-2: Enable all for performance + // { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 }, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK + { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 }, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK + { 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C }, // Misc Ctrl: Enable 8QW burst Mem Access + // { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 }, // Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 }, // Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 }, // Write Policy 1 + // { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 }, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL + // { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 }, // CPU Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 }, // Write Policy + { 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 }, // Bandwidth Timer + { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 }, // CPU Misc Ctrl + // { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B }, // CPU Miscellaneous Control 3 + // { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B }, // CPU Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A }, // CPU Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 }, // CPU Miscellaneous Control 3 + { 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 }, // CPU Miscellaneous Control 4 // Set APIC and SMRAM - 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control - 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg - 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table + { 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 }, // APIC Related Control + { 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 }, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg + { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table }; #define USE_VCP 1 /* 0 means "use DVP". */ @@ -273,7 +261,8 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { #define gCom1Base 0x3f8 #define gCom2Base 0x2f8 -void EmbedComInit(void) +#if 0 +static void EmbedComInit(void) { u8 ByteVal; u16 ComBase; @@ -379,11 +368,11 @@ void EmbedComInit(void) /* SOutput("Embedded COM output\n"); */ /* while(1); */ } +#endif /* cache_as_ram.inc jumps to here. */ void main(unsigned long bist) { - unsigned cpu_reset = 0; u16 boot_mode; u8 rambits, Data8, Data; device_t device; @@ -550,7 +539,7 @@ void main(unsigned long bist) /* * For coreboot most time of S3 resume is the same as normal boot, * so some memory area under 1M become dirty, so before this happen, - * I need to backup the content of mem to top-mem. + * I need to backup the content of mem to top-mem. * * I will reserve the 1M top-men in LBIO table in coreboot_table.c * and recovery the content of 1M-mem in wakeup.c. @@ -631,7 +620,7 @@ void main(unsigned long bist) ); #endif - /* + /* * WAKE_MEM_INFO is inited in get_set_top_available_mem() * in tables.c these two memcpy() not not be enabled if set * the MTRR around this two lines. @@ -683,8 +672,5 @@ void main(unsigned long bist) ); #endif } - #endif - } -