X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fvia%2Fepia-m%2Fromstage.c;h=7dba82c85299d2f7e99366b979f7c8f2e321e44e;hb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;hp=0a5ddbc8ae6097b42f397ef2ccd41204b50232f3;hpb=64ed2b73451de4b655b3fdda0ff42825a165c317;p=coreboot.git

diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index 0a5ddbc8a..7dba82c85 100644
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -1,16 +1,12 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#if 0
-#include <cpu/x86/lapic.h>
-#endif
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/vt8623/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -22,10 +18,6 @@
 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
 #include "southbridge/via/vt8235/vt8235_early_serial.c"
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -33,27 +25,27 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/via/vt8623/raminit.c"
 
-static void enable_mainboard_devices(void) 
+static void enable_mainboard_devices(void)
 {
 	device_t dev;
-  
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_8235), 0);
-  
+
 	if (dev == PCI_DEV_INVALID) {
 		die("Southbridge not found!!!\n");
 	}
 	pci_write_config8(dev, 0x50, 0x80);
 	pci_write_config8(dev, 0x51, 0x1f);
 #if 0
-	// This early setup switches IDE into compatibility mode before PCI gets 
+	// This early setup switches IDE into compatibility mode before PCI gets
 	// a chance to assign I/Os
 	// movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
 	// //      movb    $0x09, %dl
 	// movb    $0x00, %dl
 	// PCI_WRITE_CONFIG_BYTE
 #endif
-	/* we do this here as in V2, we can not yet do raw operations 
+	/* we do this here as in V2, we can not yet do raw operations
 	 * to pci!
 	 */
         dev += 0x100; /* ICKY */
@@ -65,7 +57,7 @@ static void enable_mainboard_devices(void)
 	pci_write_config8(dev, 0x3d, 0);
 }
 
-static void enable_shadow_ram(void) 
+static void enable_shadow_ram(void)
 {
 	device_t dev = 0; /* no need to look up 0:0.0 */
 	unsigned char shadowreg;
@@ -78,7 +70,6 @@ static void enable_shadow_ram(void)
 
 static void main(unsigned long bist)
 {
-	unsigned long x;
 	device_t dev;
 
 	/*
@@ -90,7 +81,7 @@ static void main(unsigned long bist)
 	 * Disable the firewire stuff, which apparently steps on IO 0+ on
 	 * reset. Doh!
 	 */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_6305), 0);
 	if (dev != PCI_DEV_INVALID) {
 		pci_write_config8(dev, 0x15, 0x1c);
@@ -102,14 +93,12 @@ static void main(unsigned long bist)
 
 	enable_smbus();
 
-	print_spew("In romstage.c:main()\n");
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
 	// init_timer();
 
-	outb(5, 0x80);	
+	post_code(0x05);
 
 	print_debug(" Enabling mainboard devices\n");
 	enable_mainboard_devices();
@@ -118,21 +107,14 @@ static void main(unsigned long bist)
 	enable_shadow_ram();
 
 	ddr_ram_setup((const struct mem_controller *)0);
-	
+
 	/* Check all of memory */
-#if 0
-	ram_check(0x00000000, msr.lo);
-#endif
 #if 0
 	static const struct {
 		unsigned long lo, hi;
 	} check_addrs[] = {
 		/* Check 16MB of memory @ 0*/
 		{ 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
-		/* Check 16MB of memory @ 2GB */
-		{ 0x80000000, 0x81000000 },
-#endif
 	};
 	int i;
 	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
@@ -146,7 +128,6 @@ static void main(unsigned long bist)
 	}
 
 	//dump_pci_devices();
-	
+
 	print_spew("Leaving romstage.c:main()\n");
 }
-