X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Ftyan%2Fs4882%2FConfig.lb;h=48b2597451091a4c6b6e81251d62e598154f1fb3;hb=d63085b20ef40caae1c60a7532b5243e1e30b109;hp=7f6190751d55633b830c6c0f006f05c9cb78da9a;hpb=97c4947ec9af1664e81ee797834a32d3ca2f74fe;p=coreboot.git diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 7f6190751..48b259745 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -1,247 +1,307 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses ARCH -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION - -# -# -### -### Set all of the defaults for an x86 architecture -### -# -# -### -### Build the objects we have code for in this directory. -### -##object mainboard.o -config chip.h -register "fixup_scsi" = "1" -#register "fixup_vga" = "1" +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1 + +arch i386 end ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Build the objects we have code for in this directory. ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 driver mainboard.o -#dir /drivers/lsi/53c1030 -#dir /drivers/adaptec/7902 -#dir /drivers/si/3114 -#dir /drivers/intel/82551 -#dir /drivers/ati/ragexl -#object reset.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -# -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 -# -arch i386 end -#cpu k8 end -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -mainboardinit cpu/i386/bist32.inc -ldscript /cpu/i386/entry16.lds -ldscript /cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### -if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds -else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds -end -# -#### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -# -### -### Include an id string (For safe flashing) -### -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -# -#### -#### This is the early phase of linuxBIOS startup -#### Things are delicate and we test to see if we should -#### failover to another image. -#### -#option MAX_REBOOT_CNT=2 -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end -# -### -### Setup our mtrrs -### -mainboardinit cpu/k8/earlymtrr.inc -### -### Only the bootstrap cpu makes it here. -### Failover if we need to -### -# -if USE_FALLBACK_IMAGE - mainboardinit ./failover.inc -end +if CONFIG_GENERATE_MP_TABLE object mptable.o end +if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -# -# -### -### Setup the serial port -### -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -mainboardinit cpu/i386/bist32_fail.inc -# -#### -#### O.k. We aren't just an intermediary anymore! -#### -# -### -### Romcc output -### -#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit .failover.inc + if CONFIG_USE_INIT -makerule ./failover.E - depends "$(MAINBOARD)/failover.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" -end + makerule ./auto.o + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + end -makerule ./failover.inc - depends "./romcc ./failover.E" - action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end + else -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" -end -makerule ./auto.inc - depends "./romcc ./auto.E" - action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" -end -mainboardinit cpu/k8/enable_mmx_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/k8/disable_mmx_sse.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 "mc0" - pci 0:18.0 - pci 0:18.0 - pci 0:18.0 - pci 0:18.1 - pci 0:18.2 - pci 0:18.3 - southbridge amd/amd8131 "amd8131" link 1 - pci 0:0.0 - pci 0:0.1 - pci 0:1.0 - pci 0:1.1 + makerule ./auto.inc + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" + end end - southbridge amd/amd8111 "amd8111" link 1 - pci 0:0.0 - pci 0:1.0 on - pci 0:1.1 on - pci 0:1.2 on - pci 0:1.3 on - pci 0:1.5 off - pci 0:1.6 off - pci 1:0.0 on - pci 1:0.1 on - pci 1:0.2 on - pci 1:1.0 off - superio winbond/w83627hf link 1 - pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - pnp 2e.6 off # CIR - pnp 2e.7 off # GAME_MIDI_GIPO1 - pnp 2e.8 off # GPIO2 - pnp 2e.9 off # GPIO3 - pnp 2e.a off # ACPI - pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - end -end -northbridge amd/amdk8 "mc1" - pci 0:19.0 - pci 0:19.0 - pci 0:19.0 - pci 0:19.1 - pci 0:19.2 - pci 0:19.3 +## +## Build our 16 bit and 32 bit coreboot entry code +## +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds end -northbridge amd/amdk8 "mc2" - pci 0:1a.0 - pci 0:1a.0 - pci 0:1a.0 - pci 0:1a.1 - pci 0:1a.2 - pci 0:1a.3 -end +mainboardinit cpu/x86/32bit/entry32.inc + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end -northbridge amd/amdk8 "mc3" - pci 0:1b.0 - pci 0:1b.0 - pci 0:1b.0 - pci 0:1b.1 - pci 0:1b.2 - pci 0:1b.3 + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end + +## +## Build our reset vector (This is where coreboot is entered) +## +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds -dir /pc80 -#dir /bioscall + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc -cpu k8 "cpu0" - register "across" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}" +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds end -cpu k8 "cpu1" -end +## +## Setup RAM +## + if CONFIG_USE_INIT + initobject auto.o + else + mainboardinit ./auto.inc + end -cpu k8 "cpu2" -end +## +## Include the secondary Configuration files +## +config chip.h -cpu k8 "cpu3" +# sample config for tyan/s4882 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT0 + device pci 18.0 on # northbridge + # devices on link 1, link 1 == LDT 1 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on +# chip drivers/lsi/53c1030 +# device pci 4.0 on end +# device pci 4.1 on end +# register "fw_address" = "0xfff8c000" +# end + chip drivers/pci/onboard + device pci 9.0 on end #Broadcom + device pci 9.1 on end + end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + #chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci 6.0 on end + end + chip drivers/pci/onboard + device pci 5.0 on end #SiI + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on +# chip drivers/i2c/i2cmux # pca9556 smbus mux +# device i2c 18 on #0 pca9516 2, 1 +# chip drivers/i2c/lm63 #cpu0 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #1 pca9516 1, 1 +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #2 pca9516 1, 2 +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #3 pca9516 1, 3 +# chip drivers/generic/generic #dimm 3-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 3-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 3-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 3-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #4 pca9516 1, 4 +# chip drivers/generic/generic #dimm 2-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 2-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 2-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 2-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #5 pca9516 2, 2 +# chip drivers/i2c/lm63 #cpu1 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #6 pca9516 2, 3 +# chip drivers/i2c/lm63 #cpu2 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #7 pca9516 2, 4 +# chip drivers/i2c/lm63 #cpu3 temp +# device i2c 4c on end +# end +# end +# end # i2cmux +# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... +# device i2c 2e on end +# end +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid +# device i2c 2a on end +# end +# chip drivers/generic/generic # Winbond HWM 0x92 +# device i2c 49 on end +# end +# chip drivers/generic/generic # Winbond HWM 0x94 +# device i2c 4a on end +# end +# chip drivers/generic/generic # ?? +# device i2c 69 on end +# end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 on end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 on end # dual core msr +# device pnp 0.6 on end # cache size +# device pnp 0.7 on end # tsc +# end end +