X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Ftyan%2Fs2912_fam10%2Fromstage.c;h=97c03b59df979778cfd0b906d712288a8b789cfb;hb=0864016b0d5d9d7e54f120873282967759886d95;hp=29e40602437524007677851dd225b7bcb26b985d;hpb=78acf932912669eb0eb7f7280da1b3c550035ebb;p=coreboot.git diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 29e406024..97c03b59d 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -19,25 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#define RAMINIT_SYSINFO 1 - #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 -#define QRANK_DIMM_SUPPORT 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 - -#define DBGP_DEFAULT 7 - #include #include #include @@ -46,56 +30,28 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" - -static void post_code(u8 value) { - outb(value, 0x80); -} - -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#if CONFIG_USBDEBUG_DIRECT -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" -#include "pc80/usbdebug_direct_serial.c" -#endif -#include "lib/ramtest.c" - +#include +#include +#include #include - -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" - +#include "cpu/amd/model_10xxx/apic_timer.c" +#include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" - +#include "superio/winbond/w83627hf/early_serial.c" +#include "superio/winbond/w83627hf/early_init.c" #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" - +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -103,21 +59,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" -#include "northbridge/amd/amdfam10/amdfam10_pci.c" - +#include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" - #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 - -#define MCP55_PCI_E_X_0 1 - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ @@ -126,23 +72,20 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" -#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - -#include "cpu/amd/car/copy_and_run.c" - +#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/init_cpus.c" - -#include "cpu/amd/model_10xxx/fidvid.c" +#if CONFIG_UPDATE_CPU_MICROCODE +#include "cpu/amd/model_10xxx/update_microcode.c" +#endif -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" +#include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; @@ -158,66 +101,57 @@ static void sio_setup(void) dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); - } -#include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, +#endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - u32 bsp_apicid = 0; - u32 val; - u32 wants_reset; + u32 bsp_apicid = 0, val, wants_reset; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); } post_code(0x30); - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); - printk_debug("\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG_DIRECT - mcp55_enable_usbdebug_direct(DBGP_DEFAULT); - early_usbdebug_direct_init(); -#endif - val = cpuid_eax(1); - printk_debug("BSP Family_Model: %08x\n", val); - printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - printk_debug("bsp_apicid = %02x\n", bsp_apicid); - printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); +#endif post_code(0x33); cpuSetAMDMSR(); @@ -243,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ - printk_debug("start_other_cores()\n"); + printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); @@ -251,9 +185,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if FAM10_SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -271,9 +205,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif + init_timer(); // Need to use TMICT to synconize FID/VID + wants_reset = mcp55_early_setup_x(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ @@ -284,28 +220,59 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } if (wants_reset) - printk_debug("mcp55_early_setup_x wanted additional reset!\n"); + printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ - printk_debug("fill_mem_ctrl()\n"); + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); - printk_debug("enable_smbus()\n"); + printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); - post_code(0x3E); - memreset_setup(); post_code(0x40); - printk_debug("raminit_amdmct()\n"); + printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); - printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); + printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +}