X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Ftyan%2Fs2891%2FConfig.lb;h=944b95d1fe012217351772c53fdb3679e71fe3e6;hb=b5e10bcf1fdaa684189581b65861ab6f7775c4f1;hp=67c7b3c8a905162316c88b2bf98c3d1755722703;hpb=9a791dffeae2097aa0a18f645ce07acfed41b9bc;p=coreboot.git diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 67c7b3c8a..944b95d1f 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -1,40 +1,7 @@ -## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_STREAM = 1 - -## -## Compute where this copy of linuxBIOS will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -arch i386 end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1 +arch i386 end ## ## Build the objects we have code for in this directory. @@ -51,64 +18,42 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - - if CONFIG_USE_INIT - - makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" - end - - else - - makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" - action "perl -e 's/.rodata/.rom.data/g' -pi $@" - action "perl -e 's/.text/.section .rom.text/g' -pi $@" - end - - end -else - - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +if CONFIG_USE_INIT + makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" end - +else makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end - end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds end mainboardinit cpu/x86/32bit/entry32.inc - -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -116,23 +61,16 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -if USE_DCACHE_RAM +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end ## @@ -149,24 +87,18 @@ if USE_FALLBACK_IMAGE ldscript /southbridge/nvidia/ck804/romstrap.lds end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds - if USE_DCACHE_RAM - else - mainboardinit ./failover.inc - end end ### @@ -176,190 +108,173 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - # ROMCC - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - - ## -## Include the secondary Configuration files +## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end - +config chip.h # sample config for tyan/s2891 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end end - device pci 1.1 on # SM 0 -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 54 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 55 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 56 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 57 on end -# end - end # SM -# device pci 1.1 on # SM 1 + device pci 1.1 on # SM 0 +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end + end # SM +# device pci 1.1 on # SM 1 # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 -# device i2c 2d on end -# end -# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 -# device i2c 2e on end -# end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN -# device i2c 2a on end -# end -# chip drivers/generic/generic # Winbond HWM 0x92 -# device i2c 49 on end -# end -# chip drivers/generic/generic # Winbond HWM 0x94 -# device i2c 4a on end -# end +# device i2c 2d on end +# end +# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 +# device i2c 2e on end +# end +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN +# device i2c 2a on end +# end +# chip drivers/generic/generic # Winbond HWM 0x92 +# device i2c 49 on end +# end +# chip drivers/generic/generic # Winbond HWM 0x94 +# device i2c 4a on end +# end # end #SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 7.0 on end - # register "rom_address" = "0xfff80000" #for 512K + chip drivers/pci/onboard + device pci 7.0 on end + #register "rom_address" = "0xfff80000" #for 512K register "rom_address" = "0xfff00000" #for 1M - end + end end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # Link 1 device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + chip drivers/pci/onboard + device pci 9.0 on end device pci 9.1 on end - end + end end - device pci 1.1 on end - end + device pci 1.1 on end + end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end #mc0 - + end # pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc # device pnp 0.8 on end # hard_reset -# end +# end end # root_complex