X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Ftyan%2Fs2880%2Fauto.c;h=6384f4d152423b0b6f90280659590a1e1c319757;hb=55ba88da9e4df2d47d2eba8c4e3e67a37ae06ed7;hp=d9c1f1cb9bb02577557cf1c2e03134c6d084c133;hpb=8aa7bccc9dcc51213f3b15f91f2d4985203f16dd;p=coreboot.git diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c index d9c1f1cb9..6384f4d15 100644 --- a/src/mainboard/tyan/s2880/auto.c +++ b/src/mainboard/tyan/s2880/auto.c @@ -1,41 +1,71 @@ #define ASSEMBLY 1 + #include #include -#include #include +#include #include +#include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/early_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/k8/apic_timer.c" +#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#include "cpu/p6/boot_cpu.c" +#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "debug.c" +#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void hard_reset(void) +{ + set_bios_reset(); + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); +} +static void soft2_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1); +} -#define REV_B_RESET 0 static void memreset_setup(void) { -#if REV_B_RESET==1 + if (is_cpu_pre_c0()) { outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 -#else + } + else { outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 -#endif + } outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { + if (is_cpu_pre_c0()) { udelay(800); -#if REV_B_RESET==1 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 -#endif udelay(90); + } } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) @@ -63,7 +93,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) */ uint32_t ret=0x00010101; /* default row entry */ - + /* Link1 of CPU0 to Link1 of CPU1 */ static const unsigned int rows_2p[2][2] = { { 0x00050101, 0x00010404 }, { 0x00010404, 0x00050101 } @@ -92,52 +122,18 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* include mainboard specific ht code */ -#include "hypertransport.c" - -//#include "northbridge/amd/amdk8/cpu_ldtstop.c" -//#include "southbridge/amd/amd8111/amd8111_ldtstop.c" +//#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" -static void enable_lapic(void) -{ - msr_t msr; - msr = rdmsr(0x1b); - msr.hi &= 0xffffff00; - msr.lo &= 0x000007ff; - msr.lo |= APIC_DEFAULT_BASE | (1 << 11); - wrmsr(0x1b, msr); -} +#include "northbridge/amd/amdk8/resourcemap.c" -static void stop_this_cpu(void) -{ - unsigned apicid; - apicid = apic_read(APIC_ID) >> 24; - - /* Send an APIC INIT to myself */ - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); - /* Wait for the ipi send to finish */ - apic_wait_icr_idle(); - - /* Deassert the APIC INIT */ - apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); - apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); - /* Wait for the ipi send to finish */ - apic_wait_icr_idle(); - - /* If I haven't halted spin forever */ - for(;;) { - hlt(); - } -} #define FIRST_CPU 1 #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -static void main(void) +static void main(unsigned long bist) { static const struct mem_controller cpu[] = { #if FIRST_CPU @@ -158,26 +154,45 @@ static void main(void) .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .channel0 = { (0xa<<3)|4, 0, 0, 0 }, + .channel1 = { (0xa<<3)|5, 0, 0, 0 }, }, #endif }; - if (cpu_init_detected()) { - asm("jmp __cpu_reset"); - } - enable_lapic(); - init_timer(); - if (!boot_cpu() ) { - notify_bsp_ap_is_stopped(); - stop_this_cpu(); - } - uart_init(); - console_init(); - setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); + int needs_reset; + unsigned nodeid; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + amd_early_mtrr_init(); + enable_lapic(); + init_timer(); + + nodeid = lapicid() & 0xf; + + if (cpu_init_detected(nodeid)) { + asm volatile ("jmp __cpu_reset"); + } + distinguish_cpu_resets(nodeid); + if (!boot_cpu()) { + stop_this_cpu(); + } + } + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + setup_default_resource_map(); + needs_reset = setup_coherent_ht_domain(); + needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } #if 0 print_pci_devices();