X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Ftyan%2Fs2880%2FConfig.lb;h=87d4224e861b94ff7197a431db19d3d4e56e96e1;hb=b5e10bcf1fdaa684189581b65861ab6f7775c4f1;hp=275170ac9f8bef0dc020f4b328384112c8695823;hpb=650b6d0b61087d979f18f57b64ede4ff9d1c56f6;p=coreboot.git diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 275170ac9..87d4224e8 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -1,209 +1,205 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses ARCH -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION -# -# -### -### Set all of the defaults for an x86 architecture -### -# -# -### -### Build the objects we have code for in this directory. -### -config chip.h -register "fixup_scsi" = "1" -register "fixup_vga" = "1" +include /config/nofailovercalculation.lb + +arch i386 end ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Build the objects we have code for in this directory. ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - driver mainboard.o -#driver lsi_scsi.o -#driver adaptec_scsi.o -#driver promise_sata.o -#driver intel_nic.o -#object reset.o + +#dir /drivers/si/3114 + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -# -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 -# -arch i386 end -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -mainboardinit cpu/i386/bist32.inc -ldscript /cpu/i386/entry16.lds -ldscript /cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" +end + +end +## +## Build our 16 bit and 32 bit coreboot entry code +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + +mainboardinit cpu/x86/32bit/entry32.inc + + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end + +## +## Build our reset vector (This is where coreboot is entered) +## if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end -# -#### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -# -### -### Include an id string (For safe flashing) -### + +## +## Include an id string (For safe flashing) +## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -# -#### -#### This is the early phase of linuxBIOS startup -#### Things are delicate and we test to see if we should -#### failover to another image. -#### -#option MAX_REBOOT_CNT=2 -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end -# -### -### Setup our mtrrs -### -mainboardinit cpu/k8/earlymtrr.inc + +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc + ### -### Only the bootstrap cpu makes it here. -### Failover if we need to +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. ### -# if USE_FALLBACK_IMAGE - mainboardinit ./failover.inc + ldscript /arch/i386/lib/failover.lds end -# -# ### -### Setup the serial port -### -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -mainboardinit cpu/i386/bist32_fail.inc -# -### -### Romcc output +### O.k. We aren't just an intermediary anymore! ### -makerule ./failover.E - depends "$(MAINBOARD)/failover.c" - action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" +## +## Setup RAM +## +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc end -makerule ./failover.inc - depends "./romcc ./failover.E" - action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end +## +## Include the secondary Configuration files +## +config chip.h -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" -end -makerule ./auto.inc - depends "./romcc ./auto.E" - action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" -# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" -end -mainboardinit cpu/k8/enable_mmx_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/k8/disable_mmx_sse.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 "mc0" - pci 0:18.0 - pci 0:18.0 - pci 0:18.0 - pci 0:18.1 - pci 0:18.2 - pci 0:18.3 - southbridge amd/amd8131 "amd8131" link 0 - pci 0:0.0 - pci 0:0.1 - pci 0:1.0 - pci 0:1.1 - end - southbridge amd/amd8111 "amd8111" link 0 - pci 0:0.0 - pci 0:1.0 on - pci 0:1.1 on - pci 0:1.2 on - pci 0:1.3 on - pci 0:1.5 off - pci 0:1.6 off - pci 1:0.0 on - pci 1:0.1 on - pci 1:0.2 on - pci 1:1.0 off - superio winbond/w83627hf link 1 - pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - pnp 2e.6 off # CIR - pnp 2e.7 off # GAME_MIDI_GIPO1 - pnp 2e.8 off # GPIO2 - pnp 2e.9 off # GPIO3 - pnp 2e.a off # ACPI - pnp 2e.b off # HW Monitor +# sample config for tyan/s2880 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end end end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on + chip drivers/pci/onboard + device pci 9.0 on end #broadcom + device pci 9.1 on end + end +# chip drivers/lsi/53c1030 +# device pci a.0 on end +# device pci a.1 on end +# register "fw_address" = "0xfff8c000" +# end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 5.0 on end #some sata + end + chip drivers/pci/onboard + device pci 6.0 on end #adti + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end end -northbridge amd/amdk8 "mc1" - pci 0:19.0 - pci 0:19.0 - pci 0:19.0 - pci 0:19.1 - pci 0:19.2 - pci 0:19.3 -end - - -dir /pc80 -#dir /bioscall -cpu k8 "cpu0" - register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}" -end - -cpu k8 "cpu1" -end