X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fsupermicro%2Fx6dhe_g%2Fromstage.c;h=b6c6c1d443106d8ba73feb936cddd76de7ce8ab0;hb=42fa7fe28b60b448f501e99ee285a0af12c86d34;hp=995234b808ce85a75bed8391fa781c4c74df7423;hpb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;p=coreboot.git diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 995234b80..b6c6c1d44 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -6,10 +6,9 @@ #include #include #include -#include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "southbridge/intel/esb6300/esb6300_early_smbus.c" +#include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" @@ -17,14 +16,14 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "x6dhe_g_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -35,6 +34,10 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) +static void mch_reset(void) {} +static void mainboard_set_e7520_pll(unsigned bits) {} +static void mainboard_set_e7520_leds(void) {} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -42,19 +45,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" -#include "arch/i386/lib/stages.c" +#include "arch/x86/lib/stages.c" static void main(unsigned long bist) { static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, } @@ -63,17 +60,12 @@ static void main(unsigned long bist) if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ @@ -83,16 +75,13 @@ static void main(unsigned long bist) /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing esb6300?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00); #if 0 display_cpuid_update_microcode(); -#endif -#if 0 print_pci_devices(); #endif #if 1 @@ -101,9 +90,8 @@ static void main(unsigned long bist) #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); // dump_ipmi_registers(); @@ -111,21 +99,7 @@ static void main(unsigned long bist) sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif }