X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fsunw%2Fultra40%2Fromstage.c;h=21d50469d7f8402c007e643cfcf33ebe0897414c;hb=836ae29ee325b1e3d28ff59468cc50913b1e24ce;hp=c76f802f5868eb7ee2efc4023ebe682f0cb79def;hpb=64ed2b73451de4b655b3fdda0ff42825a165c317;p=coreboot.git diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index c76f802f5..21d50469d 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -1,12 +1,3 @@ -#define K8_ALLOCATE_IO_RANGE 1 - -#define QRANK_DIMM_SUPPORT 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - - #include #include #include @@ -14,60 +5,44 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "console/console.c" -#include "lib/ramtest.c" - +#include +#include +#include +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" - #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) - #define SUPERIO_GPIO_IO_BASE 0x400 -static void sio_gpio_setup(void){ +static void memreset(int controllers, const struct mem_controller *ctrl) { } +#ifdef ENABLE_ONBOARD_SCSI +static void sio_gpio_setup(void) +{ unsigned value; /*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); - } +#endif -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static inline void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -77,17 +52,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" - - /* tyan does not want the default */ -#include "resourcemap.c" - +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" - -#define CK804_NUM 2 -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" +#include "southbridge/nvidia/ck804/early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ @@ -98,82 +65,63 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ -#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" - -#include "cpu/amd/car/copy_and_run.c" - +#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); - + byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - -#if 1 + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); - + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); - value &= 0xbf; + value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); -#endif - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -189,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset(); @@ -205,9 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); - memreset_setup(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); } -