X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fsunw%2Fultra40%2FConfig.lb;h=98b37191b95969e513ffb1d5296da067954f2950;hb=b5e10bcf1fdaa684189581b65861ab6f7775c4f1;hp=82de7c3e1cd428b03ba662dd450256d89e298d28;hpb=be13dc72d91bd3c5791fb2a3a18ee610860404ee;p=coreboot.git diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb index 82de7c3e1..98b37191b 100644 --- a/src/mainboard/sunw/ultra40/Config.lb +++ b/src/mainboard/sunw/ultra40/Config.lb @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of linuxBIOS will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1 arch i386 end @@ -47,50 +15,22 @@ object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" - action "perl -e 's/.rodata/.rom.data/g' -pi $@" - action "perl -e 's/.text/.section .rom.text/g' -pi $@" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -else - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - - makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" - end - -end - ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -99,7 +39,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -107,11 +46,9 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -121,12 +58,6 @@ else ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## @@ -141,56 +72,33 @@ if USE_FALLBACK_IMAGE ldscript /southbridge/nvidia/ck804/romstrap.lds end - - -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds - if USE_DCACHE_RAM - else - mainboardinit ./failover.inc - end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - # ROMCC - mainboardinit cpu/x86/fpu/enable_fpu.inc - mainboardinit cpu/x86/mmx/enable_mmx.inc - mainboardinit cpu/x86/sse/enable_sse.inc - mainboardinit ./auto.inc - mainboardinit cpu/x86/sse/disable_sse.inc - mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h # sample config for tyan/s2895 chip northbridge/amd/amdk8/root_complex