X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Froda%2Frk886ex%2Fromstage.c;h=109d2e81020666b5d65f28dbc5b93b6a8a04c8db;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=151e6ccea24e231d9ad319ce0d9dd01b19f9e0d1;hpb=5e32823a68f74618845c21600c8fa491f9c6c1a4;p=coreboot.git diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 151e6ccea..109d2e810 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -21,13 +21,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. - -/* Configuration of the i945 driver */ -#define CHIPSET_I945GM 1 -#define CHANNEL_XOR_RANDOMIZATION 1 -// Rocky freezing temperature settings: -#define MAXIMUM_SUPPORTED_FREQUENCY 400 - #include #include #include @@ -35,28 +28,18 @@ #include #include #include - -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" - +#include +#include #include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include #include +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" -#if CONFIG_USBDEBUG_DIRECT -#define DBGP_DEFAULT 1 -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_direct_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" - -#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void); -#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -72,19 +55,6 @@ static void setup_ich7_gpios(void) outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ @@ -102,7 +72,6 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); } - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -187,7 +156,7 @@ static void rcba_config(void) RCBA32(0x3400) = (1 << 2); /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; RCBA32(0x3418) |= (1 << 0); // Required. @@ -269,22 +238,25 @@ static void init_artec_dongle(void) #include // Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" -void real_main(unsigned long bist) +void main(unsigned long bist) { u32 reg32; int boot_mode = 0; - if (bist == 0) { + if (bist == 0) enable_lapic(); - } + + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ich7_enable_lpc(); early_superio_config(); @@ -292,9 +264,9 @@ void real_main(unsigned long bist) /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG_DIRECT - i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); - early_usbdebug_direct_init(); +#if CONFIG_USBDEBUG + i82801gx_enable_usbdebug(1); + early_usbdebug_init(); #endif console_init(); @@ -303,8 +275,9 @@ void real_main(unsigned long bist) report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); } /* Perform some early chipset initialization required @@ -334,7 +307,7 @@ void real_main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -344,8 +317,8 @@ void real_main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -357,7 +330,7 @@ void real_main(unsigned long bist) #if !CONFIG_HAVE_ACPI_RESUME #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if defined(DEBUG_RAM_SETUP) +#if CONFIG_DEBUG_RAM_SETUP sdram_dump_mchbar_registers(); { @@ -389,7 +362,7 @@ void real_main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ @@ -397,4 +370,3 @@ void real_main(unsigned long bist) } #endif } -