X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Folpc%2Frev_a%2Fromstage.c;h=fc605d1a88e22bce18e69ecd96c9c7c8b2f5727a;hb=14e22779625de673569c7b950ecc2753fb915b31;hp=1503baa6ba65cac8d63561f09b20d148f95080ca;hpb=0e1e8065e303030c39c3f2c27e5d32ee58a16c66;p=coreboot.git

diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c
index 1503baa6b..fc605d1a8 100644
--- a/src/mainboard/olpc/rev_a/romstage.c
+++ b/src/mainboard/olpc/rev_a/romstage.c
@@ -50,7 +50,7 @@ static inline unsigned int fls(unsigned int x)
 	Trrd=2 (act2act)
 	Tref=17.8ms
   */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
 	 *                      component Banks (byte 17) * module banks, side (byte 5) *
@@ -100,11 +100,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	/* timing and mode ... */
 
 	msr = rdmsr(0x20000019);
-	
-	/* per standard bios settings */	
+
+	/* per standard bios settings */
 
 	msr.hi = 0x18000108;
-	msr.lo = 
+	msr.lo =
 			(6<<28) |		// cas_lat
 			(10<<24)|		// ref2act
 			(7<<20)|		// act2pre
@@ -114,8 +114,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 			(2<<6)|			// dplwr
 			(2<<4)|			// dplrd
 			(3);			// dal
-	/* the msr value reported by quanta is very, very different. 
-	 * we will go with that value for now. 
+	/* the msr value reported by quanta is very, very different.
+	 * we will go with that value for now.
 	 */
 	msr.lo = 0x286332a3;
 
@@ -180,9 +180,9 @@ static void main(unsigned long bist)
 
 	cpuRegInit();
 	print_err("done cpuRegInit\n");
-	
+
 	sdram_initialize(1, memctrl);
-	
+
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }