X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fmsi%2Fms9185%2Fromstage.c;h=5c52dd29ddfe5d5a083f92d88374dc101a6aa507;hb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;hp=0fa6a65d869afe638b6bc8bb25b2d167a9586f8e;hpb=d28c2986d69141280fce64ac5603b107512f8771;p=coreboot.git

diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 0fa6a65d8..5c52dd29d 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -33,7 +33,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
@@ -41,19 +40,17 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <reset.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -88,38 +85,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
- /* msi does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* msi does not want the default */
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define RC0 (0x10<<8)
-#define RC1 (0x01<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
+#include <spd.h>
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
+#define RC0 (0x10<<8)
+#define RC1 (0x01<<8)
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-                       //first node
-                        RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
-                        RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
+                      //first node
+                       RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
+                       RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
                        //second node
                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
@@ -268,6 +250,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        post_cache_as_ram();
-
 }
-