X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fmsi%2Fms9185%2FConfig.lb;h=7745cf23714fc49b56ef41ab0fd07e541d6a8223;hb=6f52d11e9ee15e72c6d7ec23e1cc9f4d25dd264c;hp=856237fd55dde656f9050ab71841e512de2bba68;hpb=f8ee1806ac524bc782c93eccc59ee3c929abddb9;p=coreboot.git

diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb
index 856237fd5..7745cf237 100644
--- a/src/mainboard/msi/ms9185/Config.lb
+++ b/src/mainboard/msi/ms9185/Config.lb
@@ -22,39 +22,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
 
 arch i386 end
 
@@ -77,26 +45,23 @@ if HAVE_PIRQ_TABLE
        object irq_tables.o
 end
 
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
                # compile cache_as_ram.c to auto.o
                makerule ./cache_as_ram_auto.o
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
                end
 
        else
                #compile cache_as_ram.c to auto.inc
                makerule ./cache_as_ram_auto.inc
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-                       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
                end
 
        end
-end
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -107,7 +72,6 @@ if USE_FALLBACK_IMAGE
 end
 
 mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -115,7 +79,6 @@ if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -134,12 +97,10 @@ end
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
        ##
        ## Setup Cache-As-Ram
        ##
        mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -147,9 +108,7 @@ end
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-       if USE_DCACHE_RAM
                ldscript /arch/i386/lib/failover.lds
-       end
 end
 
 ###
@@ -159,22 +118,16 @@ end
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
                initobject cache_as_ram_auto.o
        else
                mainboardinit ./cache_as_ram_auto.inc
        end
 
-end
-
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-       config chip.h
-end
+config chip.h
 
 # sample config for amd/serengeti_cheetah
 chip northbridge/amd/amdk8/root_complex