X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fkontron%2F986lcd-m%2Fromstage.c;h=201d90378fe28f5c0cc6cccb7b3751f6fb22b90d;hb=d0835953506263b0d9218b62176693315f2ef2f3;hp=939862a3ee989b60954448a6e461f84ba97d5123;hpb=53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72;p=coreboot.git diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 939862a3e..201d90378 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -18,23 +18,10 @@ */ // __PRE_RAM__ means: use "unsigned" for device, not a struct. -#define __PRE_RAM__ - -/* Configuration of the i945 driver */ -#define CHIPSET_I945GM 1 -/* Usually system firmware turns off system memory clock signals to - * unused SO-DIMM slots to reduce EMI and power consumption. - * However, the Kontron 986LCD-M does not like unused clock signals to - * be disabled. If other similar mainboard occur, it would make sense - * to make this an entry in the sysinfo structure, and pre-initialize that - * structure in the mainboard's romstage.c main() function. For now a - * #define will do. - */ -#define OVERRIDE_CLOCK_DISABLE 1 -#define CHANNEL_XOR_RANDOMIZATION 1 #include #include +#include #include #include #include @@ -43,30 +30,23 @@ #include "superio/winbond/w83627thg/w83627thg.h" +#include #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" #include -#if CONFIG_USBDEBUG_DIRECT -#define DBGP_DEFAULT 1 -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_direct_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c" -#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void); #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -82,18 +62,6 @@ static void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ @@ -108,11 +76,10 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); // COM4 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + // io 0x300 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -121,7 +88,7 @@ static void ich7_enable_lpc(void) static void early_superio_config_w83627thg(void) { device_t dev; - + dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_ext_func_mode(dev); @@ -196,7 +163,7 @@ static void early_superio_config_w83627thg(void) pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627THG_SP2); + dev=PNP_DEV(0x4e, W83627THG_SP2); pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); @@ -251,7 +218,7 @@ static void rcba_config(void) * would essentially disable all three ethernet ports of the mainboard. * It's possible to rename the ports to achieve compatibility to the * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. + * interrupt routing information. * To avoid this, we enable (unused) port 6 and swap it with port 1 * in the case that ethernet port 1 is disabled. Since no devices * are connected to that port, we don't have to worry about interrupt @@ -361,9 +328,7 @@ static void early_ich7_init(void) // #include "lib/cbmem.c" -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { u32 reg32; int boot_mode = 0; @@ -372,15 +337,20 @@ void real_main(unsigned long bist) enable_lapic(); } + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + ich7_enable_lpc(); early_superio_config_w83627thg(); /* Set up the console */ uart_init(); -#if CONFIG_USBDEBUG_DIRECT - i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); - early_usbdebug_direct_init(); +#if CONFIG_USBDEBUG + i82801gx_enable_usbdebug(1); + early_usbdebug_init(); #endif console_init(); @@ -389,8 +359,9 @@ void real_main(unsigned long bist) report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); } /* Perform some early chipset initialization required @@ -417,7 +388,7 @@ void real_main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -427,8 +398,8 @@ void real_main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -455,6 +426,8 @@ void real_main(unsigned long bist) #endif #endif + quick_ram_check(); + MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME @@ -472,7 +445,7 @@ void real_main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */