X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fjetway%2Fj7f24%2Fromstage.c;h=b0c14968b962571c9c1b0daa685f8c9a4c7090ec;hb=0d5a6accc84530d44f35ba4f3a74b370a1f88f86;hp=0d8e9dad3b913a69154f51753f1a86dadb936c8d;hpb=64d3baf9829baf9285c94cae0406ee0f428c04c0;p=coreboot.git diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index 0d8e9dad3..b0c14968b 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -26,16 +26,15 @@ #include #include #include -#include "pc80/serial.c" -#include "console/console.c" -#include "lib/ramtest.c" +#include #include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" +#include +#include #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) @@ -54,7 +53,8 @@ static void enable_mainboard_devices(void) { device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); @@ -83,7 +83,7 @@ static const struct mem_controller ctrl = { .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) @@ -95,26 +95,13 @@ void main(unsigned long bist) uart_init(); console_init(); - print_spew("In romstage.c:main()\n"); - enable_smbus(); smbus_fixup(&ctrl); - if (bist == 0) { - print_debug("doing early_mtrr\n"); - early_mtrr_init(); - } - /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); - - /* ram_check(0, 640 * 1024); */ - - print_spew("Leaving romstage.c:main()\n"); } -