X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fiwill%2Fdk8s2%2Fromstage.c;h=f95c69c3ea1b81f27e657da1086916c89672d6ab;hb=42fa7fe28b60b448f501e99ee285a0af12c86d34;hp=b15643adaad065ad3c812fbb3f983cfe34cebdd3;hpb=d28c2986d69141280fce64ac5603b107512f8771;p=coreboot.git

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index b15643ada..f95c69c3e 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
+#include "superio/winbond/w83627hf/early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -42,13 +35,13 @@
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+		/* Set the memreset low. */
+		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Ensure the BIOS has control of the memory lines. */
+		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
 	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+		/* Ensure the CPU has control of the memory lines. */
+		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
 	}
 }
 
@@ -56,15 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 	if (is_cpu_pre_c0()) {
 		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Set memreset high. */
+		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
 		udelay(90);
 	}
 }
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -76,28 +67,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
 #include "northbridge/amd/amdk8/resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
+#include <spd.h>
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -114,26 +89,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
         int needs_reset;
         unsigned bsp_apicid = 0;
 
         if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
-
 		enumerate_ht_chain();
-
-		/* Setup the rom access for 4M */
-		amd8111_enable_rom();
         }
 
-        if (bist == 0) {
+        if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-        }
 
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        uart_init();
         console_init();
 
 	/* Halt if there was a built in self test failure */
@@ -165,26 +133,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
 #if CONFIG_SET_FIDVID
-
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
         }
-
 	enable_fid_change();
-
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
         init_fidvid_bsp(bsp_apicid);
-
         // show final fid and vid
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
                	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
         }
 #endif
 
@@ -220,6 +181,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-