X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fiwill%2Fdk8_htx%2Fromstage.c;h=75584f3090f24bbce28ee10bacd95ceef910c191;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=c3f75e8ce0178341aa266cadbab8ec6ff8e8feb7;hpb=76e8152c3924d52fc700b8eee656aa16f88f6e3a;p=coreboot.git diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index c3f75e8ce..75584f309 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,5 +1,3 @@ -#define SET_NB_CFG_54 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -13,30 +11,23 @@ #include #include #include - #include #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" - #include "cpu/x86/bist.h" - #include "lib/delay.c" - #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" - /* * GPIO28 of 8111 will control H0_MEMRESET_L * GPIO29 of 8111 will control H1_MEMRESET_L @@ -44,13 +35,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); } } @@ -59,14 +50,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl) if (is_cpu_pre_c0()) { udelay(800); /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } } -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -78,61 +67,40 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" - - /* tyan does not want the default */ #include "resourcemap.c" - #include "cpu/amd/dualcore/dualcore.c" - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - +#include #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - - // second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // first node + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // second node + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ amd8111_enable_rom(); } - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -167,26 +135,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif @@ -222,6 +183,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now - } -