X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fiwill%2Fdk8_htx%2FConfig.lb;h=b6ea0e291dc2246e0199af34e7ce8159ed22bf91;hb=b8e2027be817159d4606f991475b59fc36b0242d;hp=dd3b2ddfaa843302cae42d082f37f6a0527e7220;hpb=ef6cb094b83b2717fba379a2c6670c19b12c676d;p=coreboot.git

diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb
index dd3b2ddfa..b6ea0e291 100644
--- a/src/mainboard/iwill/dk8_htx/Config.lb
+++ b/src/mainboard/iwill/dk8_htx/Config.lb
@@ -1,50 +1,6 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
-	default ROM_SECTION_SIZE   = FAILOVER_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
-    if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
-    else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
-	default ROM_SECTION_OFFSET = 0
-    end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
-	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
-    if USE_FALLBACK_IMAGE
-	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
-    else
-	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-    end
-end
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/failovercalculation.lb
 
 arch i386 end 
 
@@ -59,25 +15,25 @@ driver mainboard.o
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE 
+if CONFIG_GENERATE_MP_TABLE 
 	object mptable.o 
 end
 
-if HAVE_PIRQ_TABLE 
+if CONFIG_GENERATE_PIRQ_TABLE 
 	object irq_tables.o 
 end
 
-#if HAVE_ACPI_TABLES
+#if CONFIG_GENERATE_ACPI_TABLES
 #       object acpi_tables.o
 #       object fadt.o
-#       if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_SB_HT_CHAIN_ON_BUS0
 #               object dsdt_bus0.o
 #       else
 #               object dsdt.o
 #       end
 #       object ssdt.o
-#       if ACPI_SSDTX_NUM
-#                if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_ACPI_SSDTX_NUM
+#                if CONFIG_SB_HT_CHAIN_ON_BUS0
 #                 object ssdt2_bus0.o
 #                else
 #                 object ssdt2.o
@@ -85,43 +41,43 @@ end
 #       end
 #end
 
-if HAVE_ACPI_TABLES
+if CONFIG_GENERATE_ACPI_TABLES
         object acpi_tables.o
         object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
+		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
 		action  "mv dsdt_lb.hex dsdt.c"
 	end
         object ./dsdt.o
 
 	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
 	
-        if ACPI_SSDTX_NUM
+        if CONFIG_ACPI_SSDTX_NUM
             makerule ssdt2.c
-                        depends "$(MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
+                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
                         action  "mv pci2.hex ssdt2.c"
             end
             object ./ssdt2.o
             makerule ssdt3.c
-                        depends "$(MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
+                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
                         action  "mv pci3.hex ssdt3.c"
             end
             object ./ssdt3.o
             makerule ssdt4.c
-                        depends "$(MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
+                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
                         action  "mv pci4.hex ssdt4.c"
             end
             object ./ssdt4.o
             makerule ssdt5.c
-                        depends "$(MAINBOARD)/dx/pci5.asl"
-                        action  "iasl -p $(PWD)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
+                        action  "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
                         action  "mv pci5.hex ssdt5.c"
             end
@@ -129,33 +85,30 @@ if HAVE_ACPI_TABLES
         end
 end
 
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		# compile cache_as_ram.c to auto.o
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" 
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else   
 		#compile cache_as_ram.c to auto.inc 
 		makerule ./cache_as_ram_auto.inc
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"         
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 
 	end
-end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
 	makerule ./apc_auto.o
-		depends "$(MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
 	end
 	ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -165,20 +118,19 @@ end
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 end
 
 mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -186,13 +138,12 @@ if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -200,7 +151,7 @@ if HAVE_FAILOVER_BOOT
 	ldscript /cpu/x86/32bit/reset32.lds 
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -215,29 +166,23 @@ end
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
-	if USE_DCACHE_RAM
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
-	end
     end
 else
-    if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
-	end
     end
 end
 
@@ -248,22 +193,16 @@ end
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject cache_as_ram_auto.o
 	else
 		mainboardinit ./cache_as_ram_auto.inc
 	end
 
-end
-
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 dir /southbridge/amd/amd8132