X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fiwave%2FiWRainbowG6%2Fdsdt.asl;h=5bf59a7d89820cd3b45752acd7485318f39cde6d;hb=91bd3068a7c28d429bb7a2581ccee40645c137c9;hp=f19ffb90437cc7bcb5a230b2463222bad0542d5c;hpb=b05bf5bca978a12a5c278bf1fbc90e7f5cff69ae;p=coreboot.git

diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl
index f19ffb904..5bf59a7d8 100644
--- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl
+++ b/src/mainboard/iwave/iWRainbowG6/dsdt.asl
@@ -30,7 +30,7 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 
 	// global NVS and variables
-	#include "../../../southbridge/intel/sch/acpi/globalnvs.asl"
+	#include <southbridge/intel/sch/acpi/globalnvs.asl>
 
 	// General Purpose Events
 	//#include "acpi/gpe.asl"
@@ -40,11 +40,11 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include "../../../northbridge/intel/sch/acpi/sch.asl"
-			#include "../../../southbridge/intel/sch/acpi/sch.asl"
+			#include <northbridge/intel/sch/acpi/sch.asl>
+			#include <southbridge/intel/sch/acpi/sch.asl>
 		}
 	}
 
 	/* Chipset specific sleep states */
-	#include "../../../southbridge/intel/sch/acpi/sleepstates.asl"
+	#include <southbridge/intel/sch/acpi/sleepstates.asl>
 }