X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Fmtarvon%2Fromstage.c;h=525f02e7a0610728234d21d7d31dbd08153619c0;hb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;hp=d5d00a9b03a317bdf5869ead3026f00d8b06856a;hpb=d41a0bc532c837705d5abc2334e1bbf9dd06eb83;p=coreboot.git

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index d5d00a9b0..525f02e7a 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -15,7 +15,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
  */
 
 #include <stdint.h>
@@ -26,30 +25,23 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
 static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);
@@ -57,10 +49,11 @@ static inline int spd_read_byte(u16 device, u8 address)
 
 #include "northbridge/intel/i3100/raminit.c"
 #include "lib/generic_sdram.c"
-#include "../jarrell/debug.c"
+#if 0 /* skip_romstage doesn't compile with gcc */
 #include "arch/i386/lib/stages.c"
+#endif
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
 	msr_t msr;
 	u16 perf;
@@ -71,21 +64,25 @@ static void main(unsigned long bist)
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
-			.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+			.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+			.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
 		}
 	};
 
 	if (bist == 0) {
+#if 0 /* skip_romstage doesn't compile with gcc */
 		/* Skip this if there was a built in self test failure */
-		early_mtrr_init();
 		if (memory_initialized()) {
 			skip_romstage();
 		}
+#endif
 	}
+
 	/* Set up the console */
 	i3100_enable_superio();
-	i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
+	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
 	uart_init();
 	console_init();
 
@@ -124,4 +121,3 @@ static void main(unsigned long bist)
 
 	ram_check(0, 1024 * 1024);
 }
-