X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Fjarrell%2Fromstage.c;h=5d33b10633841b5b8aa0c7831a1310b04fda2775;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=8b39ce58435ed755e8c2aac56c132777222886c3;hpb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;p=coreboot.git

diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 8b39ce584..5d33b1063 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -45,12 +45,6 @@ static void main(unsigned long bist)
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
-			/*
-			.f0 = PCI_DEV(0, 0x00, 0),
-			.f1 = PCI_DEV(0, 0x00, 1),
-			.f2 = PCI_DEV(0, 0x00, 2),
-			.f3 = PCI_DEV(0, 0x00, 3),
-			*/
 			.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
 			.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
 		}
@@ -59,9 +53,8 @@ static void main(unsigned long bist)
 	if (bist == 0) {
 		/* Skip this if there was a built in self test failure */
 		early_mtrr_init();
-		if (memory_initialized()) {
+		if (memory_initialized())
 			skip_romstage();
-		}
 	}
 
 	/* Setup the console */
@@ -86,9 +79,8 @@ static void main(unsigned long bist)
 	/* config LPC decode for flash memory access */
         device_t dev;
         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-        if (dev == PCI_DEV_INVALID) {
+        if (dev == PCI_DEV_INVALID)
                 die("Missing ich5?");
-        }
         pci_write_config32(dev, 0xe8, 0x00000000);
         pci_write_config8(dev, 0xf0, 0x00);
 
@@ -99,9 +91,8 @@ static void main(unsigned long bist)
 #if 0
 //	dump_spd_registers(&cpu[0]);
 	int i;
-	for(i = 0; i < 1; i++) {
+	for(i = 0; i < 1; i++)
 		dump_spd_registers();
-	}
 #endif
 	disable_watchdogs();
 	power_down_reset_check();
@@ -111,8 +102,6 @@ static void main(unsigned long bist)
 	ich5_watchdog_on();
 #if 0
 	dump_pci_devices();
-#endif
-#if 0
 	dump_pci_device(PCI_DEV(0, 0x00, 0));
 	dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif