X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Feagleheights%2Fromstage.c;h=8f8cd0f00fce34b7665e09f32a9f43f2360524ed;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=4a04b9a091bb45b34cca4db037498be3d2be2084;hpb=78acf932912669eb0eb7f7280da1b3c550035ebb;p=coreboot.git

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 4a04b9a09..8f8cd0f00 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -20,70 +20,28 @@
  * MA 02110-1301 USA
  */
 
-#define __PRE_RAM__
-
 #include <delay.h>
-
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include <cpu/x86/bist.h>
-
-#include "lib/ramtest.c"
+#include <cpu/intel/acpi.h>
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
+#include "northbridge/intel/i3100/i3100.h"
+#include "southbridge/intel/i3100/i3100.h"
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define IA32_PERF_STS     0x198
-#define IA32_PERF_CTL     0x199
-#define MSR_THERM2_CTL    0x19D
-#define IA32_MISC_ENABLES 0x1A0
-
-/* SATA */
-#define SATA_MAP 0x90
-
-#define SATA_MODE_IDE  0x00
-#define SATA_MODE_AHCI 0x01
-
-/* RCBA registers */
-#define RCBA 0xF0
-#define DEFAULT_RCBA 0xFEA00000
-
 #define RCBA_RPC   0x0224 /* 32 bit */
 
 #define RCBA_TCTL  0x3000 /*  8 bit */
@@ -104,10 +62,6 @@
 #define RCBA_FD    0x3418 /* 32 bit */
 #define RCBA_PRC   0x341C /* 32 bit */
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);
@@ -120,11 +74,12 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "lib/generic_sdram.c"
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
+#include <spd.h>
 
-#include "southbridge/intel/i3100/cmos_failover.c"
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
-void early_config(void) {
-	device_t dev;
+static void early_config(void)
+{
 	u32 gcs, rpc, fd;
 
 	/* Enable RCBA */
@@ -167,7 +122,7 @@ void early_config(void) {
 	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
 	/* int boot_mode = 0; */
 
@@ -178,18 +133,19 @@ void real_main(unsigned long bist)
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
-			.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+			.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+			.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
 		}
 	};
 
-	if (bist == 0) {
+	if (bist == 0)
 		enable_lapic();
-	}
 
 	/* Setup the console */
 	i3100_enable_superio();
-	i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
 	uart_init();
 	console_init();
 
@@ -235,6 +191,3 @@ void real_main(unsigned long bist)
 	/* Initialize memory */
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 }
-
-/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"