X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Feagleheights%2Fromstage.c;h=8e1d21236330d7eb50d3fd2a707a601b44736c3d;hb=d1a1d57adca92dd71f62dfb9363def532c3fc0e6;hp=7eb83c9153432130c9c8f8ca23a1c162f8019c6f;hpb=798ef2893c44ce3194c539c8c5db33d11e8edbac;p=coreboot.git

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 7eb83c915..8e1d21236 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -29,41 +29,17 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
@@ -102,10 +78,6 @@
 #define RCBA_FD    0x3418 /* 32 bit */
 #define RCBA_PRC   0x341C /* 32 bit */
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);
@@ -119,8 +91,10 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
-void early_config(void) {
-	device_t dev;
+#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
+
+static void early_config(void)
+{
 	u32 gcs, rpc, fd;
 
 	/* Enable RCBA */
@@ -163,7 +137,7 @@ void early_config(void) {
 	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
 	/* int boot_mode = 0; */
 
@@ -185,7 +159,9 @@ void real_main(unsigned long bist)
 
 	/* Setup the console */
 	i3100_enable_superio();
-	i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
+
 	uart_init();
 	console_init();
 
@@ -232,6 +208,3 @@ void real_main(unsigned long bist)
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 }
 
-/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
-