X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Feagleheights%2Fromstage.c;h=774f88f60f027c5ae01a5f90569796b4249d59ab;hb=361bd10bcea5db98cfc573987023449c2f59287d;hp=072dad67f847c5620cef211e7ff0b2b4e3949aae;hpb=0fe6e9a9a4dfdabf0ad1336112207899b868ee9c;p=coreboot.git

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 072dad67f..774f88f60 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,6 +33,7 @@
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/acpi.h>
 
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
@@ -44,11 +45,6 @@
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define IA32_PERF_STS     0x198
-#define IA32_PERF_CTL     0x199
-#define MSR_THERM2_CTL    0x19D
-#define IA32_MISC_ENABLES 0x1A0
-
 /* SATA */
 #define SATA_MAP 0x90