X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Feagleheights%2Fmptable.c;h=2c814d9e49916bc64a1a87a442f46167c16bf78c;hb=f9892166d548d523911263a4a2a550cd03a3309d;hp=5ee1d1f44b772b00eb733eb3430c15c5eacc32f9;hpb=c5b87c8f895502b235e1619a23bd89dda955000e;p=coreboot.git diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 5ee1d1f44..2c814d9e4 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -20,9 +20,9 @@ * MA 02110-1301 USA */ - #include #include +#include #include #include #include @@ -60,9 +60,6 @@ static void *smp_write_config_table(void *v) { - static const char sig[4] = "PCMP"; - static const char oem[8] = "COREBOOT"; - static const char productid[12] = "EagleHeights"; struct mp_config_table *mc; unsigned char bus_num, bus_chipset, bus_isa, bus_pci; unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; @@ -80,21 +77,8 @@ static void *smp_write_config_table(void *v) rcba = res->base; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - memset(mc, 0, sizeof(*mc)); - - memcpy(mc->mpc_signature, sig, sizeof(sig)); - mc->mpc_length = sizeof(*mc); /* initially just the header */ - mc->mpc_spec = 0x04; - mc->mpc_checksum = 0; /* not yet computed */ - memcpy(mc->mpc_oem, oem, sizeof(oem)); - memcpy(mc->mpc_productid, productid, sizeof(productid)); - mc->mpc_oemptr = 0; - mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ - mc->mpc_lapic = LAPIC_ADDR; - mc->mpe_length = 0; - mc->mpe_checksum = 0; - mc->reserved = 0; + + mptable_init(mc, "EagleHeights", LAPIC_ADDR); smp_write_processors(mc); @@ -144,46 +128,13 @@ static void *smp_write_config_table(void *v) smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); - /* - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 3, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 4, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 5, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - } - */ + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); + mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1); /* Internal PCI device for i3100 */