X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fintel%2Fd945gclf%2Fromstage.c;h=8d155d1662a58263bb2c9cd7d3079e5790b6cbc3;hb=57b2ff886e0ce2c92820f5722c8031def3ac94cf;hp=131145cfb9abe9a2952df91a8fe1c665b07b064b;hpb=c02b4fc9db3c3c1e263027382697b566127f66bb;p=coreboot.git

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 131145cfb..8d155d166 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -18,11 +18,6 @@
  */
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
-#define __PRE_RAM__
-
-/* Configuration of the i945 driver */
-#define CHIPSET_I945GC 1
-#define CHANNEL_XOR_RANDOMIZATION 1
 
 #include <stdint.h>
 #include <string.h>
@@ -31,33 +26,22 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
+#include <lib.h>
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
-
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG_DIRECT
-#define DBGP_DEFAULT 1
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_direct_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void enable_smbus(void);
+
+void setup_ich7_gpios(void)
 {
 	/* TODO: This is highly board specific and should be moved */
 	printk(BIOS_DEBUG, " GPIOS...");
@@ -74,19 +58,6 @@ static void setup_ich7_gpios(void)
 	outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/reset_test.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
@@ -99,7 +70,6 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
@@ -108,7 +78,7 @@ static void ich7_enable_lpc(void)
 static void early_superio_config_lpc47m15x(void)
 {
 	device_t dev;
-	
+
 	dev=PNP_DEV(0x2e, LPC47M15X_SP1);
 	pnp_enter_conf_state(dev);
 
@@ -216,8 +186,6 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include "southbridge/intel/i82801gx/cmos_failover.c"
-
 #include <cbmem.h>
 
 // Now, this needs to be included because it relies on the symbol
@@ -228,7 +196,7 @@ static void early_ich7_init(void)
 //
 #include "lib/cbmem.c"
 
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
 	u32 reg32;
 	int boot_mode = 0;
@@ -243,9 +211,9 @@ void real_main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG_DIRECT
-	i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
-	early_usbdebug_direct_init();
+#if CONFIG_USBDEBUG
+	i82801gx_enable_usbdebug(1);
+	early_usbdebug_init();
 #endif
 
 	console_init();
@@ -281,7 +249,7 @@ void real_main(unsigned long bist)
 
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
-	
+
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 	dump_spd_registers();
 #endif
@@ -291,8 +259,8 @@ void real_main(unsigned long bist)
 	/* Perform some initialization that must run before stage2 */
 	early_ich7_init();
 
-	/* This should probably go away. Until now it is required 
-	 * and mainboard specific 
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
 	 */
 	rcba_config();
 
@@ -304,7 +272,7 @@ void real_main(unsigned long bist)
 
 #if !CONFIG_HAVE_ACPI_RESUME
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 	sdram_dump_mchbar_registers();
 #endif
 
@@ -336,13 +304,11 @@ void real_main(unsigned long bist)
 		 * memory completely, but that's a wonderful clean up task for another
 		 * day.
 		 */
-		if (resume_backup_memory) 
-			memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
 		/* Magic for S3 resume */
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
 	}
 #endif
 }
-
-#include "cpu/intel/model_106cx/cache_as_ram_disable.c"