X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fibm%2Fe326%2Fromstage.c;h=68e62918788356fe1fa606fe160f4605be5b1a01;hb=1f7d3c5672ec90f8d71907b1a07c8a87fa461047;hp=1202001fdba27ba9b2dbe9a4bf048215bf8b390d;hpb=6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23;p=coreboot.git

diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 1202001fd..68e629187 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -8,39 +8,34 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87366/pc87366_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 #include <spd.h>
 
+#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
+
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+		/* Set the memreset low. */
+		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		/* Ensure the BIOS has control of the memory lines. */
+		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+		/* Ensure the CPU has control of the memory lines. */
+		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
 	}
 }
 
@@ -48,35 +43,26 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 	if (is_cpu_pre_c0()) {
 		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		/* Set memreset high. */
+		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
 		udelay(90);
 	}
 }
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -109,15 +95,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
-
 		enumerate_ht_chain();
-
-		amd8111_enable_rom();
         }
 
-        if (bist == 0) {
+        if (bist == 0)
 		init_cpus(cpu_init_detectedx);
-        }
 
 	pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
@@ -148,6 +130,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
-
 }
-