X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fhp%2Fdl165_g6_fam10%2Fromstage.c;h=32a94d425bc8f795192ae7e130ec9f815b5be9fe;hb=5ff7c13e858a31addf1558731a12cf6c753b576d;hp=c2f5ac0d676e91bda95a9fe22344658444970d73;hpb=00e1460a8367c4199358034064329abcfb7e5c28;p=coreboot.git diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index c2f5ac0d6..32a94d425 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -28,14 +28,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include #include #include @@ -47,34 +39,27 @@ #include "option_table.h" #include #include -#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include - +#include #include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - -#include "superio/serverengines/pilot/pilot_early_serial.c" -#include "superio/serverengines/pilot/pilot_early_init.c" -#include "superio/nsc/pc87417/pc87417_early_serial.c" - +#include "superio/serverengines/pilot/early_serial.c" +#include "superio/serverengines/pilot/early_init.c" +#include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - //#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" - static inline void activate_spd_rom(const struct mem_controller *ctrl) { u8 val; @@ -92,59 +77,57 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/amdfam10_pci.c" - +#include "northbridge/amd/amdfam10/pci.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE #include "cpu/amd/model_10xxx/update_microcode.c" -#include "cpu/amd/model_10xxx/init_cpus.c" +#endif +#include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "spd_addr.h" +static const u8 spd_addr[] = { + // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr; - + if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ + /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - bcm5785_enable_rom(); bcm5785_enable_lpc(); - //enable RTC - pc87417_enable_dev(RTC_DEV); + pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } post_code(0x30); - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - console_init(); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV val = cpuid_eax(1); @@ -156,7 +139,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); +#endif post_code(0x33); cpuSetAMDMSR(); @@ -187,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -236,3 +221,37 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +}