X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fhp%2Fdl145_g3%2Fromstage.c;h=ff16b3f8bb29068f43daf5f06acf0919b041f7f8;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=64b1c79b7213609b7e9fd1ca3b167b12f7e9a947;hpb=78acf932912669eb0eb7f7280da1b3c550035ebb;p=coreboot.git diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 64b1c79b7..ff16b3f8b 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -25,30 +25,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#define RAMINIT_SYSINFO 1 - -#define K8_ALLOCATE_IO_RANGE 1 - -#define QRANK_DIMM_SUPPORT 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -//used by init_cpus and fidvid -#define K8_SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include #include #include @@ -57,49 +37,29 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" - - -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" - +#include +#include #include - #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" - #include "superio/serverengines/pilot/pilot_early_serial.c" #include "superio/serverengines/pilot/pilot_early_init.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" - - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/debug.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" - +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -116,38 +76,15 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" - -//#include "resourcemap.c" - +#include #include "cpu/amd/dualcore/dualcore.c" - -//first node -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -//second node -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - -#include "cpu/amd/car/copy_and_run.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "northbridge/amd/amdk8/early_ht.c" #if 0 @@ -191,54 +128,43 @@ static void setup_early_ipmi_serial() void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + // first node + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - int needs_reset; - unsigned bsp_apicid = 0; - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - bcm5785_enable_rom(); - bcm5785_enable_lpc(); - //enable RTC - pc87417_enable_dev(RTC_DEV); - } - + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + int needs_reset; + unsigned bsp_apicid = 0; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + bcm5785_enable_rom(); + bcm5785_enable_lpc(); + pc87417_enable_dev(RTC_DEV); /* Enable RTC */ + } - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - //setup_mp_resource_map(); - uart_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - console_init(); // setup_early_ipmi_serial(); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV - print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); - - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -260,11 +186,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); -#if K8_SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); @@ -273,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); } #endif @@ -282,7 +208,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } @@ -292,14 +218,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID + // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); - } -