X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fhp%2Fdl145_g3%2Fromstage.c;h=eeac3e5b6a7bbce59543b2aaf9b7b5cd3164c899;hb=39124dd6c5f577861c16b947088ac1fd31169b8f;hp=2e4d4109dfe1ea4f2186834bac0fbcc30f07bff9;hpb=d6532116c94c705c7e94a34ab2f046e431fb3682;p=coreboot.git

diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 2e4d4109d..eeac3e5b6 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -25,27 +25,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
-#define K8_ALLOCATE_IO_RANGE 1
-
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
-#define DBGP_DEFAULT 7
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -54,43 +37,28 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "superio/serverengines/pilot/pilot_early_serial.c"
 #include "superio/serverengines/pilot/pilot_early_init.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
 
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -111,28 +79,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
+#include <spd.h>
 #include "cpu/amd/dualcore/dualcore.c"
-
-//first node
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-//second node
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 #if 0
@@ -177,34 +128,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// first node
-		 DIMM0, DIMM2, 0, 0,
-		 DIMM1, DIMM3, 0, 0,
-
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// second node
 		DIMM4, DIMM6, 0, 0,
 		DIMM5, DIMM7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE 
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
 	int needs_reset;
 	unsigned bsp_apicid = 0;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
-
 		enumerate_ht_chain();
-		bcm5785_enable_rom();
 		bcm5785_enable_lpc();
-		//enable RTC
-		pc87417_enable_dev(RTC_DEV);
+		pc87417_enable_dev(RTC_DEV); /* Enable RTC */
 	}
 
-	if (bist == 0) {
+	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	}
 
 	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
@@ -239,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 	bcm5785_early_setup();
 
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
@@ -279,4 +224,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-