X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fgigabyte%2Fm57sli%2Fromstage.c;h=7665c7b622303a19888e416b20c062414b69c025;hb=6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23;hp=d606040d2c879d4890f8cba2c04139e6ecd70bb4;hpb=86a571797d9ede9d79edcfdce38f50a80b9a49f9;p=coreboot.git

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index d606040d2..7665c7b62 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -35,6 +35,7 @@
 
 #include <console/console.h>
 #include <usbdebug.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -131,11 +132,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE