X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fgigabyte%2Fga_2761gxdk%2Fromstage.c;h=4b31b545afd59253435f4ce33dd4783267e1b164;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=5aee58d867c9626a23440fc8c5a3583b061d7b18;hpb=12584e2bd2ec7ab1ed60dc524574c8ae04dc17d6;p=coreboot.git diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 5aee58d86..4b31b545a 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -21,27 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - -#define K8_ALLOCATE_IO_RANGE 1 - -#define QRANK_DIMM_SUPPORT 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include #include #include @@ -50,49 +33,31 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" - +#include #include -#if CONFIG_USBDEBUG_DIRECT -#include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c" -#include "pc80/usbdebug_direct_serial.c" -#endif -#include "lib/ramtest.c" - +#include +#include #include - +#include "southbridge/sis/sis966/sis966.h" #include "southbridge/sis/sis966/sis966_early_smbus.c" #include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/sis/sis966/sis966_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) -#include "southbridge/sis/sis966/sis966_early_ctrl.c" - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -104,9 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" - #include "resourcemap.c" - #include "cpu/amd/dualcore/dualcore.c" #define SIS966_NUM 1 @@ -124,16 +87,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include "southbridge/sis/sis966/sis966_early_setup_ss.h" -#include "southbridge/sis/sis966/sis966_early_setup_car.c" - - - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -157,35 +113,29 @@ static void sio_setup(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, - // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the sis966 */ sis966_enable_rom(); } - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x23, 0); @@ -199,9 +149,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if CONFIG_USBDEBUG_DIRECT - sis966_enable_usbdebug_direct(DBGP_DEFAULT); - early_usbdebug_direct_init(); +#if CONFIG_USBDEBUG + sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + early_usbdebug_init(); #endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -227,27 +177,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 - +#if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif @@ -275,6 +218,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sis_init_stage2(); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now - } -