X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fasus%2Fm5a99x-evo%2Fdevicetree.cb;h=06760a9858dddfd945268813beda6ebeae224249;hb=2143d3737553b293923ad566ef4cda3aec742f75;hp=623f0f9120872bf7736e2422ffb2e7d26b012f68;hpb=e16bee4a7c7723b45d72de29aea496a23fa32028;p=coreboot.git

diff --git a/src/mainboard/asus/m5a99x-evo/devicetree.cb b/src/mainboard/asus/m5a99x-evo/devicetree.cb
index 623f0f912..06760a985 100644
--- a/src/mainboard/asus/m5a99x-evo/devicetree.cb
+++ b/src/mainboard/asus/m5a99x-evo/devicetree.cb
@@ -8,31 +8,28 @@ chip northbridge/amd/amdfam10/root_complex
 	device pci_domain 0 on
 		subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id.
 		chip northbridge/amd/amdfam10
-			device pci 18.0 on #  northbridge
-				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
-					device pci 3.0 off end # PCIE P2P bridge 0x960b
-					device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
-					device pci 5.0 off end # PCIE P2P bridge 0x9605
-					device pci 6.0 off end # PCIE P2P bridge 0x9606
-					device pci 7.0 off end # PCIE P2P bridge 0x9607
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					device pci 9.0 on end # Ethernet
-					device pci a.0 on end # Ethernet
-					register "gppsb_configuration" = "4"	# Configuration E
-					register "gpp_configuration" = "3"	# Configuration D
-					register "port_enable" = "0x6f6"
-					register "gfx_dev2_dev3" = "0"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-					register "gfx_tmds" = "1"
-					register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
-					register "gfx_ddi_config" = "1"  # Lanes 0-3 DDI_SL
-				end
+            device pci 18.0 on end # Link 0
+            device pci 18.0 on     # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1)
+                chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
+                    device pci 0.0 on  end # HT Root Complex
+                    device pci 0.1 off end # CLKCONFIG
+                    device pci 2.0 on  end # GPP1 Port0
+                    device pci 3.0 off end # GPP1 Port1
+                    device pci 4.0 off end # GPP3a Port0
+                    device pci 5.0 off end # GPP3a Port1
+                    device pci 6.0 off end # GPP3a Port2
+                    device pci 7.0 off end # GPP3a Port3
+                    device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
+                    device pci 9.0 off end # GPP3a Port4
+                    device pci a.0 off end # GPP3a Port5
+                    device pci b.0 off end # GPP2 Port0 (Not for sr5650)
+                    device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
+                    device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
+                    register "gpp1_configuration" = "0"   # Configuration 16:0 default
+                    register "gpp2_configuration" = "1"   # Configuration 8:8
+                    register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
+                    register "port_enable" = "0x2104"
+                end # northbridge/amd/cimx/rd890
 				chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pci bus
 					device pci 11.0 on end # SATA
 					device pci 12.0 on end # USB