X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fasus%2Fa8n_e%2Fromstage.c;h=155f414668272179382d5ead33a03ee3aee878ed;hb=6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23;hp=ac328c70b388a50e76b79eab1504b16b6a04da89;hpb=853263b963b4cacb4f7fa3a7f2c68dcbd094f1d7;p=coreboot.git

diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index ac328c70b..155f41466 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -24,13 +24,6 @@
 /* Used by it8712f_enable_serial(). */
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 
-/* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS == 1
-#define SET_NB_CFG_54 1
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -38,35 +31,24 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-/* Used by ck894_early_setup(). */
-#define CK804_NUM 1
-
 #include <cpu/amd/model_fxx_rev.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
-
-static void memreset_setup(void)
-{
-	/* Nothing to do. */
-}
+#include <spd.h>
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -91,7 +73,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -113,11 +94,11 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
@@ -131,9 +112,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 
 		sio_setup();
-
-		/* Setup the ck804 */
-		ck804_enable_rom();
 	}
 
 	if (bist == 0)
@@ -181,7 +159,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_smbus_registers();
 #endif
 
-	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
 #if 0