X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Fasrock%2F939a785gmh%2Fromstage.c;h=6ab8c83156914bbd7e93d1ca6e1bc249f036ad5d;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=8060b4a3d65dc91bcd83a41e3573ba758760f67c;hpb=12584e2bd2ec7ab1ed60dc524574c8ae04dc17d6;p=coreboot.git

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 8060b4a3d..6ab8c8315 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -18,20 +18,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-#define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
-#define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -41,24 +30,20 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
+#include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
-
+#include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
@@ -67,17 +52,9 @@
 #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
 
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-/*called in raminit_f.c */
 static inline int spd_read_byte(u32 device, u32 address)
 {
 	return smbus_read_byte(device, address);
@@ -89,16 +66,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_init(void)
@@ -116,7 +87,6 @@ static void sio_init(void)
 	pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
 	pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
 
-
 //idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
 //val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
 
@@ -162,14 +132,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
 		enumerate_ht_chain();
-
 		/* sb700_lpc_port80(); */
 		sb700_pci_port80();
 	}
 
-	if (bist == 0) {
+	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	}
 
 	enable_rs780_dev8();
 	sb700_lpc_init();
@@ -177,6 +145,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sio_init();
 	w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
+
+#if CONFIG_USBDEBUG
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+	early_usbdebug_init();
+#endif
+
 	console_init();
 
 	/* Halt if there was a built in self test failure */
@@ -203,8 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Check to see if processor is capable of changing FIDVID  */
 	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
 	cpuid1 = cpuid(0x80000007);
-	if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -216,7 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
@@ -244,4 +216,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-