X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fmainboard%2Farima%2Fhdama%2FOptions.lb;h=b7de4eb6d46a68f9a5374fce3af3d633c506e4b9;hb=9dd27bc03a53f69b55c1c9718a5e44365019c082;hp=2f2df1c8ec1552e88bee9da7e1308e6584e15198;hpb=6e53f50082cfac4ec2d06d2ff6515781190ad1c0;p=coreboot.git diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb index 2f2df1c8e..b7de4eb6d 100644 --- a/src/mainboard/arima/hdama/Options.lb +++ b/src/mainboard/arima/hdama/Options.lb @@ -1,159 +1,182 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CBFS +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_STREAM -uses CONFIG_ROM_STREAM_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses COREBOOT_EXTRA_VERSION +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_CROSS_COMPILE uses CC uses HOSTCC -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_OBJCOPY +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_LOGICAL_CPUS +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_USE_INIT +uses CONFIG_USE_PRINTK_IN_CAR ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_LOGICAL_CPUS enables dual core support ## -default ROM_SIZE=524288 +default CONFIG_LOGICAL_CPUS=1 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default FALLBACK_SIZE=131072 +default CONFIG_ROM_SIZE=524288 ## -## Build code for the fallback boot +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_FALLBACK_SIZE=0x40000 ## -## Build code to reset the motherboard from linuxBIOS +## Build code for the fallback boot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## -## Funky hard reset implementation -## -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=4 -default HARD_RESET_FUNCTION=0 +## Build code to reset the motherboard from coreboot +## +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=2 ## ## Build code to setup a generic IOAPIC ## default CONFIG_IOAPIC=1 +## +## enable CACHE_AS_RAM specifics +## +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=0 + +#VGA +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="HDAMA" -default MAINBOARD_VENDOR="ARIMA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +default CONFIG_MAINBOARD_VENDOR="ARIMA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM ## -default CONFIG_ROM_STREAM = 1 +default CONFIG_ROM_PAYLOAD = 1 ### ### Defaults of options that you may want to override in the target config file @@ -162,9 +185,16 @@ default CONFIG_ROM_STREAM = 1 ## ## The default compiler ## -default CC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC="gcc" +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +default CONFIG_USE_PRINTK_IN_CAR=1 + ## ## The Serial Console ## @@ -173,24 +203,24 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately @@ -199,17 +229,22 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb +# +# CBFS +# +# +default CONFIG_CBFS=0 end